diff -Naur u-boot-1.3.3/Makefile u-boot-1.3.3_cs-e9302/Makefile --- u-boot-1.3.3/Makefile 2008-05-19 12:47:11.000000000 +0200 +++ u-boot-1.3.3_cs-e9302/Makefile 2008-06-13 10:41:55.000000000 +0200 @@ -2108,6 +2108,9 @@ TQM834x_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x +cs-e9302_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t cs-e9302 NULL ep93xx + @echo "... configured for Olimex CS-E9302" ######################################################################### ## MPC85xx Systems diff -Naur u-boot-1.3.3/board/cs-e9302/Makefile u-boot-1.3.3_cs-e9302/board/cs-e9302/Makefile --- u-boot-1.3.3/board/cs-e9302/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/board/cs-e9302/Makefile 2008-06-13 10:41:55.000000000 +0200 @@ -0,0 +1,51 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := cs-e9302.o +SOBJS := flash_cfg.o pll_cfg.o sdram_cfg.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -Naur u-boot-1.3.3/board/cs-e9302/config.mk u-boot-1.3.3_cs-e9302/board/cs-e9302/config.mk --- u-boot-1.3.3/board/cs-e9302/config.mk 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/board/cs-e9302/config.mk 2008-06-13 10:41:55.000000000 +0200 @@ -0,0 +1,7 @@ +# SDRAM on the CS-E9302 is mapped at +# 0x00000000 - 0x007fffff +# 0x01000000 - 0x017fffff +# 0x04000000 - 0x047fffff +# 0x05000000 - 0x057fffff +# +TEXT_BASE = 0x05400000 diff -Naur u-boot-1.3.3/board/cs-e9302/cs-e9302.c u-boot-1.3.3_cs-e9302/board/cs-e9302/cs-e9302.c --- u-boot-1.3.3/board/cs-e9302/cs-e9302.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/board/cs-e9302/cs-e9302.c 2008-06-13 10:59:41.000000000 +0200 @@ -0,0 +1,82 @@ +/* + * vim: set ts=4 sw=4 noet: + */ +/* + * (C) Copyright 2002 2003 + * Network Audio Technologies, Inc. + * Adam Bezanson + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* set UARTBAUD bit to drive UARTs with 14.7456MHz instead of + * 14.7456/2 MHz + */ + SYSCON_PWRCNT |= 0x20000000; + + /* Machine number, as defined in linux/arch/arm/tools/mach-types + */ + //gd->bd->bi_arch_number = 1172; + gd->bd->bi_arch_number = 538; // EBD9302 + + /* adress of boot parameters + */ + gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR; + + /* We have a console + */ + gd->have_console = 1; + + return (0); +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int *src, *dst; + int i; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE_1; + + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_SIZE_2; + + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_SIZE_3; + + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_SIZE_4; + + /* copy exception vectors to 0x0 */ + src = (unsigned int*)_armboot_start; + dst = 0x0; + for (i = 0; i < 16; i++) + *dst++ = *src++; + + return (0); +} diff -Naur u-boot-1.3.3/board/cs-e9302/flash_cfg.S u-boot-1.3.3_cs-e9302/board/cs-e9302/flash_cfg.S --- u-boot-1.3.3/board/cs-e9302/flash_cfg.S 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/board/cs-e9302/flash_cfg.S 2008-06-13 10:41:55.000000000 +0200 @@ -0,0 +1,36 @@ +/* + * Flash setup for Olimex CS-E9302 board + * + * Copyright (C) 2006 Dominic Rath + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +.globl flash_cfg +flash_cfg: + /* configure smc bank 6 (Intel TE28F128J3D75 Strata Flash) + * ebibrkdis: 0, mw: 0x1 (16 bit), pme: 0, wp: 0, wst2: 2(+1), wst1: 5(+1), rble: 1, idcy: 2(+1) + * TODO: we don't enable page mode for now + */ + ldr r0, =SMC_BCR6 + ldr r1, =0x100014a2 + str r1, [r0] + + mov pc, lr diff -Naur u-boot-1.3.3/board/cs-e9302/pll_cfg.S u-boot-1.3.3_cs-e9302/board/cs-e9302/pll_cfg.S --- u-boot-1.3.3/board/cs-e9302/pll_cfg.S 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/board/cs-e9302/pll_cfg.S 2008-06-13 10:41:55.000000000 +0200 @@ -0,0 +1,56 @@ +/* + * PLL setup for Olimex CS-E9302 board + * + * Copyright (C) 2006 Dominic Rath + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +.globl pll_cfg +pll_cfg: + /* configure PLL1 + * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2 + * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000, pll1_x2: 331776000.000000, pll1_out: 331776000.000000 + */ + ldr r0, =SYSCON_BASE + ldr r1, =0x02b49907 + str r1, [r0, #0x20] /* SYSCON_CLKSET1 */ + + /* flush the pipeline + * writing to CLKSET1 causes the EP9302 to enter standby for between 8 ms to 16 ms, until PLL1 stabilizes + */ + nop + nop + nop + nop + nop + + /* configure PLL2 + * usb_div: 4, nbyp2: 1, pll2_en: 1 + * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000, pll2_x2: 384000000.000000, pll2_out: 192000000.000000 + */ + ldr r1, =0x300dc317 + str r1, [r0, #0x24] /* SYSCON_CLKSET1 */ + + /* the user's guide recommends to wait at least 1 ms for PLL2 to stabilize, + * but Cirrus' Redboot doesn't do that, either + */ + + mov pc, lr diff -Naur u-boot-1.3.3/board/cs-e9302/sdram_cfg.S u-boot-1.3.3_cs-e9302/board/cs-e9302/sdram_cfg.S --- u-boot-1.3.3/board/cs-e9302/sdram_cfg.S 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/board/cs-e9302/sdram_cfg.S 2008-06-13 10:41:55.000000000 +0200 @@ -0,0 +1,121 @@ +/* + * SDRAM setup for Olimex CS-E9302 board + * + * Copyright (C) 2006 Dominic Rath + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +/* delay for 200us + * loop takes 4 cycles at 6.02ns per cycle = 24.1ns + * 0x3000 (12288) gives us 296us to be safe + */ +.macro delay200 + ldr r0, =0x3000 +200: + subs r0, r0, #1 + bne 200b +.endm + +.globl sdram_cfg +sdram_cfg: + /* 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM + * + * CLK cycle time min: + * @ CAS latency = 3: 7.5ns + * @ CAS latency = 2: 10ns + * We're running at 66MHz (15ns cycle time) external bus speed (HCLK), + * so it's safe to use CAS latency = 2 + * + * RAS-to-CAS delay min: + * 20ns + * At 15ns cycle time, we use RAS-to-CAS delay = 2 + * + * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear + * as four blocks of 8MB size, instead of eight blocks of 4MB size: + * 0x00000000 - 0x007fffff + * 0x01000000 - 0x017fffff + * 0x04000000 - 0x047fffff + * 0x05000000 - 0x057fffff + * + * BANKCOUNT = 1: This is a device with four banks + */ + ldr r0, =0x0021002c + ldr r1, =SDRAM_BASE + str r0, [r1, #0x1c] /* SDRAMCFG3 */ + + /* Issue continous NOP commands */ + ldr r0, =(GLOBALCFG_INIT | GLOBALCFG_MRS | GLOBALCFG_CKE) + str r0, [r1, #0x04] /* SDRAMGLOBALCFG */ + + delay200 + + /* Errata for EP9302 rev. E0 says that PRECHARGE ALL isn't always issued + * Do a read from each bank to make sure they're precharged + * Logical address bits A[22:21] map to BA[1:0] (SROMLL is set) + * The errata further says that this isn't going to be fixed, + * therefor do it for all revisions + */ + ldr r0, =(GLOBALCFG_CKE) + str r0, [r1, #0x4] /* SDRAMGLOBALCFG */ + + ldr r0, =0x00000000 /* A[22:21] = b00 */ + str r0, [r0] + ldr r0, =0x00200000 /* A[22:21] = b01 */ + str r0, [r0] + ldr r0, =0x00400000 /* A[22:21] = b10 */ + str r0, [r0] + ldr r0, =0x00600000 /* A[22:21] = b11 */ + str r0, [r0] + + /* Load refresh timer with 10 to issue refresh every 10 cycles */ + ldr r0, =0x0a + str r0, [r1, #0x08] /* SDRAMREFRESHTIMER */ + + /* Wait at least 80 clock cycles to provide 8 refresh cycles to all SDRAMs */ + delay200 /* we wait 200us, which is a lot more than necessary */ + + /* Program refresh timer with normal value + * We need 8192 refresh cycles every 64ms at 15ns per cycle: + * 64ms / 8192 = 7.8125us + * 7.8125us / 15ns = 520 (0x208) + */ + ldr r0, =0x208 + str r0, [r1, #0x08] /* SDRAMREFRESHTIMER */ + + /* Select mode register update mode */ + ldr r0, =(GLOBALCFG_CKE | GLOBALCFG_MRS) + str r0, [r1, #0x04] /* SDRAMGLOBALCFG */ + + /* Program mode register + * A[22:09] is output as SYA[13:0] on a 16 bit ext. bus + * CAS latency: 2 + * Burst type: sequential + * Burst length: 8 (required for 16 bit ext. bus) + * SYA[13:0] = 0x0023 + */ + ldr r0, =0x00004600 + ldr r0, [r0] + + /* Select normal operation mode */ + ldr r0, =(GLOBALCFG_CKE) + str r0, [r1, #0x04] /* SDRAMGLOBALCFG */ + + mov pc, lr diff -Naur u-boot-1.3.3/board/cs-e9302/u-boot.lds u-boot-1.3.3_cs-e9302/board/cs-e9302/u-boot.lds --- u-boot-1.3.3/board/cs-e9302/u-boot.lds 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/board/cs-e9302/u-boot.lds 2008-06-13 10:41:55.000000000 +0200 @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + . = 0x1000; + LONG(0x53555243) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -Naur u-boot-1.3.3/cpu/arm920t/ep93xx/Makefile u-boot-1.3.3_cs-e9302/cpu/arm920t/ep93xx/Makefile --- u-boot-1.3.3/cpu/arm920t/ep93xx/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/cpu/arm920t/ep93xx/Makefile 2008-06-13 10:41:55.000000000 +0200 @@ -0,0 +1,55 @@ +# vim: set ts=8 sw=8 noet: +# +# Cirrus Logic EP93xx CPU-specific Makefile +# +# Copyright (C) 2004, 2005 +# Cory T. Tusar, Videon Central, Inc., +# +# Copyright (C) 2006 +# Dominic Rath +# +# Based on an original Makefile, which is +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 675 Mass Ave, Cambridge, MA 02139, USA. +# +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = cpu.o eth.o interrupts.o speed.o +SOBJS = lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff -Naur u-boot-1.3.3/cpu/arm920t/ep93xx/cpu.c u-boot-1.3.3_cs-e9302/cpu/arm920t/ep93xx/cpu.c --- u-boot-1.3.3/cpu/arm920t/ep93xx/cpu.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/cpu/arm920t/ep93xx/cpu.c 2008-06-13 10:41:55.000000000 +0200 @@ -0,0 +1,113 @@ +/* vim: set ts=8 sw=8 noet: + * + * Cirrus Logic EP93xx CPU-specific support. + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include + +#if defined(CONFIG_EP93XX) +#include + + +/* The errata for silicon revision E1 states that the PartID of the + * ExtensionID register is not programmed, and that this feature has been + * removed from the chip. + * + * Note also that the chip revision indication found in the CHIP_ID register + * (0x80930094) has proven reliable for determining a particular core's + * silicon version. + */ +extern int checkcpu(void) +{ + printf("CPU: Cirrus Logic EP93xx"); + printf(" - Rev. "); + switch (SYSCON_CHIPID & 0xF0000000) { + case 0x00000000: + printf("A"); + break; + + case 0x10000000: + printf("B"); + break; + + case 0x20000000: + printf("C"); + break; + + case 0x30000000: + printf("D0"); + break; + + case 0x40000000: + printf("D1"); + break; + + case 0x50000000: + printf("E0"); + break; + + default: + printf("?"); + break; + } + + return(0); +} + + +/* All EP93xx variants have 16 KiB I-cache. */ +extern int checkicache(void) +{ + return(16 << 10); +} + + +/* All EP93xx variants have 16 KiB D-cache. */ +extern int checkdcache(void) +{ + return(16 << 10); +} + + +/* This is a nop on ARM, and is included here for completeness only. */ +extern void upmconfig(unsigned int upm, unsigned int *table, unsigned int size) +{ + /* nop */ +} + + +/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */ +extern void reset_cpu(ulong addr) +{ + /* Unlock DeviceCfg and write '1' */ + SYSCON_SYSSWLOCK = 0xAA; + SYSCON_DEVICECFG |= (1 << 31); + + /* Unlock DeviceCfg and write '0' */ + SYSCON_SYSSWLOCK = 0xAA; + SYSCON_DEVICECFG &= ~(1 << 31); + + /* Dying... */ + while(1); +} + + +#endif /* defined(CONFIG_EP93XX) */ diff -Naur u-boot-1.3.3/cpu/arm920t/ep93xx/eth.c u-boot-1.3.3_cs-e9302/cpu/arm920t/ep93xx/eth.c --- u-boot-1.3.3/cpu/arm920t/ep93xx/eth.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/cpu/arm920t/ep93xx/eth.c 2008-06-13 10:41:55.000000000 +0200 @@ -0,0 +1,891 @@ +/* vim: set ts=8 sw=8 noet: + * + * Cirrus Logic EP93xx ethernet MAC / MII driver. + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver, + * which is + * + * (C) Copyright 2002 2003 + * Adam Bezanson, Network Audio Technologies, Inc. + * + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include + + +/** + * Send an error message to the terminal. + */ +#define ERROR(x) \ +do { \ + char *__foo = strrchr(__FILE__, '/'); \ + \ + printf("%s: %d: %s(): ", (__foo == NULL ? __FILE__ : (__foo + 1)), \ + __LINE__, __FUNCTION__); \ + printf x; printf("\n"); \ +} while (0); + + +/** + * Send a trace message to the terminal. + */ +#if 0 +#define TRACE(x) \ +do { \ + char *__foo = strrchr(__FILE__, '/'); \ + \ + printf("%s: %d: %s(): ", (__foo == NULL ? __FILE__ : (__foo + 1)), \ + __LINE__, __FUNCTION__); \ + printf x; printf("\n"); \ +} while (0); + +#else +#define TRACE(x) +#endif + + +/* ----------------------------------------------------------------------------- + * EP93xx ethernet MAC functionality + */ +#if defined(CONFIG_DRIVER_EP93XX_MAC) + +/** + * #define this to dump device status and queue info during initialization and + * following errors. + */ +#undef EP93XX_MAC_DEBUG + +/** + * Number of descriptor and status entries in our RX queues. + * It must be power of 2 ! + */ +#define NUMRXDESC (8) + +/** + * Number of descriptor and status entries in our TX queues. + */ +#define NUMTXDESC (1) + +/** + * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT) + */ +#define TXSTARTMAX (944) + + +/** + * Ethernet MAC interface return values for public functions. + */ +enum eth_status { + ETH_STATUS_SUCCESS = 0, + ETH_STATUS_FAILURE = 1, +}; + + +/** + * Receive descriptor queue entry + */ +struct rx_descriptor_t { + union { + uint32_t word1; + + struct { + unsigned buffer_address : 32; + }; + }; + + union { + uint32_t word2; + + struct { + unsigned buffer_length : 16; + unsigned buffer_index : 15; + unsigned not_sof : 1; + }; + }; +} __attribute__((packed)); + +typedef struct rx_descriptor_t rx_descriptor_t; + + +/** + * Receive status queue entry + */ +struct rx_status_t { + union { + uint32_t word1; + + struct { + unsigned : 8; + unsigned hti : 6; + unsigned : 1; + unsigned crci : 1; + unsigned crce : 1; + unsigned edata : 1; + unsigned runt : 1; + unsigned fe : 1; + unsigned oe : 1; + unsigned rx_err : 1; + unsigned am : 2; + unsigned : 4; + unsigned eob : 1; + unsigned eof : 1; + unsigned rwe : 1; + unsigned rfp : 1; + }; + }; + + union { + uint32_t word2; + + struct { + unsigned frame_length : 16; + unsigned buffer_index : 15; + unsigned rfp : 1; + }; + }; +} __attribute__((packed)); + +typedef struct rx_status_t rx_status_t; + + +/** + * Transmit descriptor queue entry + */ +struct tx_descriptor_t +{ + union { + uint32_t word1; + + struct { + unsigned buffer_address : 32; + }; + }; + + union { + uint32_t word2; + + struct { + unsigned buffer_length : 12; + unsigned : 3; + unsigned abort_frame : 1; + unsigned buffer_index : 15; + unsigned eof : 1; + }; + }; +} __attribute__((packed)); + +typedef struct tx_descriptor_t tx_descriptor_t; + + +/** + * Transmit status queue entry + */ +struct tx_status_t { + union { + uint32_t word1; + + struct { + unsigned tbi : 15; + unsigned : 1; + unsigned ncoll : 5; + unsigned : 3; + unsigned ecoll : 1; + unsigned txu : 1; + unsigned ow : 1; + unsigned : 1; + unsigned lcrs : 1; + unsigned fa : 1; + unsigned txwe : 1; + unsigned txfp : 1; + }; + }; +} __attribute__((packed)); + +typedef struct tx_status_t tx_status_t; + + +/** + * Transmit descriptor queue + */ +struct tx_descriptor_queue_t { + tx_descriptor_t *base; + tx_descriptor_t *current; + tx_descriptor_t *end; +}; + +typedef struct tx_descriptor_queue_t tx_descriptor_queue_t; + + +/** + * Transmit status queue + */ +struct tx_status_queue_t { + tx_status_t *base; + tx_status_t *current; + tx_status_t *end; +}; + +typedef struct tx_status_queue_t tx_status_queue_t; + + +/** + * Receive descriptor queue + */ +struct rx_descriptor_queue_t { + rx_descriptor_t *base; + rx_descriptor_t *current; + rx_descriptor_t *end; +}; + +typedef struct rx_descriptor_queue_t rx_descriptor_queue_t; + + +/** + * Receive status queue + */ +struct rx_status_queue_t { + rx_status_t *base; + rx_status_t *current; + rx_status_t *end; +}; + +typedef struct rx_status_queue_t rx_status_queue_t; + + +/** + * EP93xx MAC private data structure + */ +struct ep93xx_mac { + int is_initialized; + + rx_descriptor_queue_t rx_dq; + rx_status_queue_t rx_sq; + void * rx_buffer[NUMRXDESC]; + + tx_descriptor_queue_t tx_dq; + tx_status_queue_t tx_sq; +}; + + +/* ep93xx_miiphy ops forward declarations */ +static int ep93xx_miiphy_read(char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short * const value); +static int ep93xx_miiphy_write(char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short const value); + + +/* Reserve memory for the MAC's private data */ +static struct ep93xx_mac dev = { 0 }; + + +/** + * Dump ep93xx_mac values to the terminal. + */ +extern inline void dump_dev(void) +{ +#if defined(EP93XX_MAC_DEBUG) + int i; + + printf("\ndump_dev()\n"); + printf(" is_initialized %02X\n", dev.is_initialized); + printf(" rx_dq.base %08X\n", dev.rx_dq.base); + printf(" rx_dq.current %08X\n", dev.rx_dq.current); + printf(" rx_dq.end %08X\n", dev.rx_dq.end); + printf(" rx_sq.base %08X\n", dev.rx_sq.base); + printf(" rx_sq.current %08X\n", dev.rx_sq.current); + printf(" rx_sq.end %08X\n", dev.rx_sq.end); + + for (i = 0; i < NUMRXDESC; i++) { + printf(" rx_buffer[%2.d] %08X\n", i, NetRxPackets[i]); + } + + printf(" tx_dq.base %08X\n", dev.tx_dq.base); + printf(" tx_dq.current %08X\n", dev.tx_dq.current); + printf(" tx_dq.end %08X\n", dev.tx_dq.end); + printf(" tx_sq.base %08X\n", dev.tx_sq.base); + printf(" tx_sq.current %08X\n", dev.tx_sq.current); + printf(" tx_sq.end %08X\n", dev.tx_sq.end); +#endif /* defined(EP93XX_MAC_DEBUG) */ +} + + +/** + * Dump all RX descriptor queue entries to the terminal. + */ +extern inline void dump_rx_descriptor_queue(void) +{ +#if defined(EP93XX_MAC_DEBUG) + int i; + + printf("\ndump_rx_descriptor_queue()\n"); + printf(" descriptor address word1 word2\n"); + for (i = 0; i < NUMRXDESC; i++) { + printf(" [ %08X ] %08X %08X\n", + (dev.rx_dq.base + i), + (dev.rx_dq.base + i)->word1, + (dev.rx_dq.base + i)->word2); + } +#endif /* defined(EP93XX_MAC_DEBUG) */ +} + + +/** + * Dump all RX status queue entries to the terminal. + */ +extern inline void dump_rx_status_queue(void) +{ +#if defined(EP93XX_MAC_DEBUG) + int i; + + printf("\ndump_rx_status_queue()\n"); + printf(" descriptor address word1 word2\n"); + for (i = 0; i < NUMRXDESC; i++) { + printf(" [ %08X ] %08X %08X\n", + (dev.rx_sq.base + i), + (dev.rx_sq.base + i)->word1, + (dev.rx_sq.base + i)->word2); + } +#endif /* defined(EP93XX_MAC_DEBUG) */ +} + + +/** + * Dump all TX descriptor queue entries to the terminal. + */ +extern inline void dump_tx_descriptor_queue(void) +{ +#if defined(EP93XX_MAC_DEBUG) + int i; + + printf("\ndump_tx_descriptor_queue()\n"); + printf(" descriptor address word1 word2\n"); + for (i = 0; i < NUMTXDESC; i++) { + printf(" [ %08X ] %08X %08X\n", + (dev.tx_dq.base + i), + (dev.tx_dq.base + i)->word1, + (dev.tx_dq.base + i)->word2); + } +#endif /* defined(EP93XX_MAC_DEBUG) */ +} + + +/** + * Dump all TX status queue entries to the terminal. + */ +extern inline void dump_tx_status_queue(void) +{ +#if defined(EP93XX_MAC_DEBUG) + int i; + + printf("\ndump_tx_status_queue()\n"); + printf(" descriptor address word1\n"); + for (i = 0; i < NUMTXDESC; i++) { + printf(" [ %08X ] %08X\n", + (dev.rx_sq.base + i), + (dev.rx_sq.base + i)->word1); + } +#endif /* defined(EP93XX_MAC_DEBUG) */ +} + + +/** + * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until + * it's cleared. + */ +static void ep93xx_mac_reset(void) +{ + TRACE(("+ep93xx_mac_reset")); + + MAC_SELFCTL |= SELFCTL_RESET; + while (MAC_SELFCTL & SELFCTL_RESET) { + /* nop */ + } + + TRACE(("-ep93xx_mac_reset")); +} + + +/** + * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL + * registers. + */ +extern void eth_halt(void) +{ + TRACE(("+eth_halt")); + + MAC_RXCTL = 0x00000000; + MAC_TXCTL = 0x00000000; + + TRACE(("-eth_halt")); +} + +#if defined(CONFIG_MII) +extern int ep93xx_miiphy_initialize(bd_t * const bd) +{ + miiphy_register("ep93xx_eth0", ep93xx_miiphy_read, ep93xx_miiphy_write); + return 0; +} +#endif + +/** + * Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are + * allocated, if necessary, for the TX and RX descriptor and status queues, + * as well as for received packets. The EP93XX MAC hardware is initialized. + * Transmit and receive operations are enabled. + */ +extern int eth_init(bd_t * const bd) +{ + int ret = ETH_STATUS_FAILURE; + int i; + + TRACE(("+eth_init")); + + /* Parameter check */ + if (bd == NULL) { + ERROR(("NULL bd")); + goto eth_init_failed_0; + } + + /* Reset the MAC */ + ep93xx_mac_reset(); + + /* Allocate space for the queues and RX packet buffers if we're not + * already initialized */ + if (!dev.is_initialized) { + if ((dev.tx_dq.base = calloc(NUMTXDESC, + sizeof(tx_descriptor_t))) == NULL) { + ERROR(("calloc() failed")); + goto eth_init_failed_0; + } + + if ((dev.tx_sq.base = calloc(NUMTXDESC, + sizeof(tx_status_t))) == NULL) { + ERROR(("calloc() failed")); + goto eth_init_failed_1; + } + + if ((dev.rx_dq.base = calloc(NUMRXDESC, + sizeof(rx_descriptor_t))) == NULL) { + ERROR(("calloc() failed")); + goto eth_init_failed_2; + } + + if ((dev.rx_sq.base = calloc(NUMRXDESC, + sizeof(rx_status_t))) == NULL) { + ERROR(("calloc() failed")); + goto eth_init_failed_3; + } + + /* Set is_initialized flag so we don't go through allocation + * portion of init again. */ + dev.is_initialized = 1; + } + + /* Reset the descriptor queues' current and end address values */ + dev.tx_dq.current = dev.tx_dq.base; + dev.tx_dq.end = (dev.tx_dq.base + NUMTXDESC); + + dev.tx_sq.current = dev.tx_sq.base; + dev.tx_sq.end = (dev.tx_sq.base + NUMTXDESC); + + dev.rx_dq.current = dev.rx_dq.base; + dev.rx_dq.end = (dev.rx_dq.base + NUMRXDESC); + + dev.rx_sq.current = dev.rx_sq.base; + dev.rx_sq.end = (dev.rx_sq.base + NUMRXDESC); + + /* Set the transmit descriptor and status queues' base address, + * current address, and length registers. Set the maximum frame + * length and threshold. Enable the transmit descriptor processor. */ + MAC_TXDQBADD = (uint32_t)dev.tx_dq.base; + MAC_TXDQCURADD = (uint32_t)dev.tx_dq.base; + MAC_TXDQBLEN = (sizeof(tx_descriptor_t) * NUMTXDESC); + + MAC_TXSTSQBADD = (uint32_t)dev.tx_sq.base; + MAC_TXSTSQCURADD = (uint32_t)dev.tx_sq.base; + MAC_TXSTSQBLEN = (sizeof(tx_status_t) * NUMTXDESC); + + MAC_TXDTHRSHLD = 0x00040000; + + MAC_TXSTSTHRSHLD = 0x00040000; + + MAC_MAXFRMLEN = (TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16); + MAC_BMCTL = BMCTL_TXEN; + + /* Set the receive descriptor and status queues' base address, + * current address, and length registers. Enable the receive + * descriptor processor. */ + MAC_RXDQBADD = (uint32_t)dev.rx_dq.base; + MAC_RXDQCURADD = (uint32_t)dev.rx_dq.base; + MAC_RXDQBLEN = (sizeof(rx_descriptor_t) * NUMRXDESC); + + MAC_RXSTSQBADD = (uint32_t)dev.rx_sq.base; + MAC_RXSTSQCURADD = (uint32_t)dev.rx_sq.base; + MAC_RXSTSQBLEN = (sizeof(rx_status_t) * NUMRXDESC); + + MAC_RXDTHRSHLD = 0x00040000; + + MAC_BMCTL = BMCTL_RXEN; + + MAC_RXSTSTHRSHLD = 0x00040000; + + /* Wait until the receive descriptor processor is active */ + while (!(MAC_BMSTS & BMSTS_RXACT)) { + /* nop */ + } + + /* Initialize the RX descriptor queue. Clear the TX descriptor queue. + * Clear the RX and TX status queues. Enqueue the RX descriptor and + * status entries to the MAC. */ + for (i = 0; i < NUMRXDESC; i++) { + (dev.rx_dq.base + i)->buffer_address = + (uint32_t)NetRxPackets[i]; + (dev.rx_dq.base + i)->buffer_length = PKTSIZE_ALIGN; + (dev.rx_dq.base + i)->buffer_index = 0; + } + + memset(dev.tx_dq.base, 0, (sizeof(tx_descriptor_t) * NUMTXDESC)); + memset(dev.rx_sq.base, 0, (sizeof(rx_status_t) * NUMRXDESC)); + memset(dev.tx_sq.base, 0, (sizeof(tx_status_t) * NUMTXDESC)); + + MAC_RXDENQ = NUMRXDESC; + MAC_RXSTSENQ = NUMRXDESC; + + /* Set the primary MAC address */ + MAC_AFP = AFP_IAPRIMARY; + MAC_INDAD = (bd->bi_enetaddr[0] | + (bd->bi_enetaddr[1] << 8) | + (bd->bi_enetaddr[2] << 16) | + (bd->bi_enetaddr[3] << 24)); + MAC_INDAD_UPPER = (bd->bi_enetaddr[4] | (bd->bi_enetaddr[5] << 8)); + + /* Turn on RX and TX */ + MAC_RXCTL = (RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON | RXCTL_RCRCA | RXCTL_MA); + MAC_TXCTL = TXCTL_STXON; + + /* Dump data structures if we're debugging */ + dump_dev(); + dump_rx_descriptor_queue(); + dump_rx_status_queue(); + dump_tx_descriptor_queue(); + dump_tx_status_queue(); + + /* Done! */ + ret = ETH_STATUS_SUCCESS; + goto eth_init_done; + + free(dev.rx_sq.base); + /* Fall through */ + +eth_init_failed_3: + free(dev.rx_dq.base); + /* Fall through */ + +eth_init_failed_2: + free(dev.tx_sq.base); + /* Fall through */ + +eth_init_failed_1: + free(dev.tx_dq.base); + /* Fall through */ + +eth_init_failed_0: +eth_init_done: + TRACE(("-eth_init %d", ret)); + return(ret); +} + + +/** + * Copy a frame of data from the MAC into the protocol layer for further + * processing. + * + * TODO: Enhance this to deal with as many packets as are available at + * the MAC at one time? */ +extern int eth_rx(void) +{ + int ret = ETH_STATUS_FAILURE; + + TRACE(("+eth_rx")); + + if (dev.rx_sq.current->rfp ) { + if ( dev.rx_sq.current->rwe) { + /* We have a good frame. Extract the frame's length + * from the current rx_status_queue entry, and copy + * the frame's data into NetRxPackets[] of the + * protocol stack. We track the total number of + * bytes in the frame (nbytes_frame) which will be + * used when we pass the data off to the protocol + * layer via NetReceive(). */ + NetReceive(dev.rx_dq.current->buffer_address, + dev.rx_sq.current->frame_length ); + TRACE(("reporting %d bytes...\n", + dev.rx_sq.current->frame_length)); + + ret = ETH_STATUS_SUCCESS; + + } else { + /* Do we have an erroneous packet? */ + ERROR(("packet rx error, status %08X %08X", + dev.rx_sq.current->word1, + dev.rx_sq.current->word2)); + dump_rx_descriptor_queue(); + dump_rx_status_queue(); + } + + /* Clear the associated status queue entry, and + * increment our current pointers to the next RX + * descriptor and status queue entries (making sure + * we wrap properly). */ + memset(dev.rx_sq.current, 0, sizeof(rx_status_t)); + + dev.rx_sq.current++; + if (dev.rx_sq.current >= dev.rx_sq.end) + dev.rx_sq.current = dev.rx_sq.base; + + dev.rx_dq.current++; + if (dev.rx_dq.current >= dev.rx_dq.end) { + dev.rx_dq.current = dev.rx_dq.base; + } + + /* Finally, return the RX descriptor and status entries + * back to the MAC engine, and loop again, checking for + * more descriptors to process. */ + MAC_RXDENQ = 1; + MAC_RXSTSENQ = 1; + } else { + ret = ETH_STATUS_SUCCESS; + } + + TRACE(("-eth_rx %d", ret)); + return(ret); +} + + +/** + * Send a block of data via ethernet. + * + * TODO: Enhance this to deal with as much data as are available at one time? */ +extern int eth_send(volatile void * const packet, int const length) +{ + int ret = ETH_STATUS_FAILURE; + + TRACE(("+eth_send")); + + /* Parameter check */ + if (packet == NULL) { + ERROR(("NULL packet")); + goto eth_send_failed_0; + } + + /* Initialize the TX descriptor queue with the new packet's info. + * Clear the associated status queue entry. Enqueue the packet + * to the MAC for transmission. */ + dev.tx_dq.current->buffer_address = (uint32_t)packet; + dev.tx_dq.current->buffer_length = length; + dev.tx_dq.current->buffer_index = 0; + dev.tx_dq.current->eof = 1; + + dev.tx_sq.current->word1 = 0; + + MAC_TXDENQ = 1; + + /* Wait for TX to complete, and check status entry for errors. */ + while (!(MAC_INTSTSC & INTSTS_TXSQ)) { + /* nop */ + } + + if (!dev.tx_sq.current->txfp || !dev.tx_sq.current->txwe) { + ERROR(("packet tx error, status %08X", + dev.tx_sq.current->word1)); + dump_tx_descriptor_queue(); + dump_tx_status_queue(); + + /* TODO: Add better error handling? */ + goto eth_send_failed_0; + } + + ret = ETH_STATUS_SUCCESS; + /* Fall through */ + +eth_send_failed_0: + TRACE(("-eth_send %d", ret)); + return(ret); +} +#endif /* defined(CONFIG_DRIVER_EP93XX_MAC) */ + + +/* ----------------------------------------------------------------------------- + * EP93xx ethernet MII functionality. + */ +#if defined(CONFIG_MII) + +/** + * Maximum MII address we support + */ +#define MII_ADDRESS_MAX (31) + +/** + * Maximum MII register address we support + */ +#define MII_REGISTER_MAX (31) + + +/** + * Ethernet MII interface return values for public functions. + */ +enum mii_status { + MII_STATUS_SUCCESS = 0, + MII_STATUS_FAILURE = 1, +}; + + +/** + * Read a 16-bit value from an MII register. + */ +static int ep93xx_miiphy_read(char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short * const value) +{ + int ret = MII_STATUS_FAILURE; + uint32_t self_ctl; + + TRACE(("+ep93xx_miiphy_read")); + + /* Parameter checks */ + if (dev == NULL) { + ERROR(("NULL dev")); + goto ep93xx_miiphy_read_failed_0; + } + + if (addr > MII_ADDRESS_MAX) { + ERROR(("invalid addr, 0x%02X", addr)); + goto ep93xx_miiphy_read_failed_0; + } + + if (reg > MII_REGISTER_MAX) { + ERROR(("invalid reg, 0x%02X", reg)); + goto ep93xx_miiphy_read_failed_0; + } + + if (value == NULL) { + ERROR(("NULL value")); + goto ep93xx_miiphy_read_failed_0; + } + + /* Save the current SelfCTL register value. Set MAC to suppress + * preamble bits. Wait for any previous MII command to complete + * before issuing the new command. */ + self_ctl = MAC_SELFCTL; +#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) + MAC_SELFCTL = (self_ctl & ~(1 << 8)); +#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ + + while (MAC_MIISTS & MIISTS_BUSY) { + /* nop */ + } + + /* Issue the MII 'read' command. Wait for the command to complete. + * Read the MII data value. */ + MAC_MIICMD = (MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | + (uint32_t)reg); + while (MAC_MIISTS & MIISTS_BUSY) { + /* nop */ + } + + *value = (unsigned short)MAC_MIIDATA; + + /* Restore the saved SelfCTL value and return. */ + MAC_SELFCTL = self_ctl; + + ret = MII_STATUS_SUCCESS; + /* Fall through */ + +ep93xx_miiphy_read_failed_0: + TRACE(("-ep93xx_miiphy_read")); + return(ret); +} + + +/** + * Write a 16-bit value to an MII register. + */ +static int ep93xx_miiphy_write(char * const dev, unsigned char const addr, + unsigned char const reg, unsigned short const value) +{ + int ret = MII_STATUS_FAILURE; + uint32_t self_ctl; + + TRACE(("+ep93xx_miiphy_write")); + + /* Parameter checks */ + if (dev == NULL) { + ERROR(("NULL dev")); + goto ep93xx_miiphy_write_failed_0; + } + + if (addr > MII_ADDRESS_MAX) { + ERROR(("invalid addr, 0x%02X", addr)); + goto ep93xx_miiphy_write_failed_0; + } + + if (reg > MII_REGISTER_MAX) { + ERROR(("invalid reg, 0x%02X", reg)); + goto ep93xx_miiphy_write_failed_0; + } + + /* Save the current SelfCTL register value. Set MAC to suppress + * preamble bits. Wait for any previous MII command to complete + * before issuing the new command. */ + self_ctl = MAC_SELFCTL; +#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) + MAC_SELFCTL = (self_ctl & ~(1 << 8)); +#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ + + while (MAC_MIISTS & MIISTS_BUSY) { + /* nop */ + } + + /* Issue the MII 'write' command. Wait for the command to complete. */ + MAC_MIIDATA = (uint32_t)value; + MAC_MIICMD = (MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | + (uint32_t)reg); + while (MAC_MIISTS & MIISTS_BUSY) { + /* nop */ + } + + /* Restore the saved SelfCTL value and return. */ + MAC_SELFCTL = self_ctl; + + ret = MII_STATUS_SUCCESS; + /* Fall through */ + +ep93xx_miiphy_write_failed_0: + TRACE(("-ep93xx_miiphy_write")); + return(ret); +} +#endif /* defined(CONFIG_MII) */ + diff -Naur u-boot-1.3.3/cpu/arm920t/ep93xx/interrupts.c u-boot-1.3.3_cs-e9302/cpu/arm920t/ep93xx/interrupts.c --- u-boot-1.3.3/cpu/arm920t/ep93xx/interrupts.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/cpu/arm920t/ep93xx/interrupts.c 2008-06-13 10:41:55.000000000 +0200 @@ -0,0 +1,172 @@ +/* vim: set ts=8 sw=8 noet: + * + * Cirrus Logic EP93xx interrupt support. + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support, + * author unknown. + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include + +#if defined(CONFIG_EP93XX) +#include +#include + + + +int interrupt_init(void); +void reset_timer(void); +ulong get_timer(ulong base); +void set_timer(ulong t); +void udelay(unsigned long usec); +void reset_timer_masked(void); +ulong get_timer_masked(void); +void udelay_masked(unsigned long usec); +unsigned long long get_ticks(void); +ulong get_tbclk(void); + + +int timer_load_val = 0; + +/* macro to read the 16 bit timer */ +static inline ulong READ_TIMER(void) +{ + return (TIMER1_VALUE & 0xffff); +} + +static ulong timestamp; +static ulong lastdec; + + +/** + * Initialize interrupt support. + */ +int interrupt_init(void) +{ + TIMER1_CONTROL = 0x00; /* use timer 1 with 2KHz and free running */ + if (timer_load_val == 0) { + /* + * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 + * (default) and prescaler = 16. Should be 10390 + * @33.25MHz and 15625 @ 50 MHz + */ + timer_load_val = 21; /* set to constant just now, until I resolve clocking issues */ + } + /* auto load, manual update of Timer 1 */ + lastdec = TIMER1_LOAD = timer_load_val; + TIMER1_CONTROL = 0xC0; /* Enable the timer and periodic mode */ + + return (0); +} + +/* + * timer without interrupts + */ + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +void udelay(unsigned long usec) +{ + ulong tmo; + + tmo = usec / 1000; + tmo *= (timer_load_val * 100); + tmo /= 1000; + + tmo += get_timer(0); + + while (get_timer_masked() < tmo) + /*NOP*/; +} + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER(); + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + ulong now = READ_TIMER(); + + if (lastdec >= now) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + timer_load_val - now; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked(unsigned long usec) +{ + ulong tmo; + + tmo = usec / 1000; + tmo *= (timer_load_val * 100); + tmo /= 1000; + + reset_timer_masked(); + + while (get_timer_masked() < tmo) + /*NOP*/; +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = timer_load_val * 100; + return tbclk; +} + + +#endif /* defined(CONFIG_EP93XX) */ diff -Naur u-boot-1.3.3/cpu/arm920t/ep93xx/lowlevel_init.S u-boot-1.3.3_cs-e9302/cpu/arm920t/ep93xx/lowlevel_init.S --- u-boot-1.3.3/cpu/arm920t/ep93xx/lowlevel_init.S 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/cpu/arm920t/ep93xx/lowlevel_init.S 2008-06-13 10:41:55.000000000 +0200 @@ -0,0 +1,68 @@ +/* + * Low-level initialization for EP93xx + * + * Copyright (C) 2006 Dominic Rath + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +.globl lowlevel_init +lowlevel_init: + + /* Turn on both LEDs */ + ldr r1, =GPIO_PEDR + ldr r0, [r1] + orr r0, r0, #(0x1 | 0x2) + str r0, [r1] + + /* backup return address */ + ldr r1, =SYSCON_SCRATCH0 + str lr, [r1] + + /* Configure flash wait states before we switch to the PLL */ + bl flash_cfg + + /* Set up PLL */ + bl pll_cfg + + /* Turn off the Green LED and leave the Red LED on */ + ldr r1, =GPIO_PEDR + ldr r0, [r1] + bic r0, r0, #(0x1) + str r0, [r1] + + /* Setup SDRAM */ + bl sdram_cfg + + /* Turn on Green LED, Turn off the Red LED */ + ldr r1, =GPIO_PEDR + ldr r0, [r1] + bic r0, r0, #(0x2) + orr r0, r0, #(0x1) + str r0, [r1] + + /* restore return address */ + ldr r1, =SYSCON_SCRATCH0 + ldr lr, [r1] + + mov pc, lr diff -Naur u-boot-1.3.3/cpu/arm920t/ep93xx/speed.c u-boot-1.3.3_cs-e9302/cpu/arm920t/ep93xx/speed.c --- u-boot-1.3.3/cpu/arm920t/ep93xx/speed.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/cpu/arm920t/ep93xx/speed.c 2008-06-13 10:41:55.000000000 +0200 @@ -0,0 +1,79 @@ +/* vim: set ts=8 sw=8 noet: + * + * Cirrus Logic EP93xx PLL support. + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * Based on the S3C24x0 speed.c, which is + * + * (C) Copyright 2001-2002 + * Wolfgang Denk, DENX Software Engineering, + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include + +/* ------------------------------------------------------------------------- */ +/* NOTE: This describes the proper use of this file. + * + * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. + * + * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of + * the specified bus in HZ. + */ +/* ------------------------------------------------------------------------- */ + +static ulong get_PLLCLK(int pllreg) +{ + /* to be implemented */ + return 0; +} + +/* return FCLK frequency */ +/* the parameter here is to force lookup on trunk 0 or trunk 1 of the clock tree + * independent from what the chip is programmed to. to just get FCLK pass in something other then 0 + */ +ulong get_FCLK(int trunk) +{ + /* to be implemented */ + return 0; +} + + +/* return HCLK frequency */ +ulong get_HCLK(void) +{ + /* to be implemented */ + return 0; +} + +ulong get_UART_PCLK(void) +{ + /* to be implemented */ + return 0; +} + +ulong get_TIMER_PCLK(void) +{ + /* to be implemented */ + return 0; +} diff -Naur u-boot-1.3.3/include/asm-arm/arch-ep93xx/ep93xx.h u-boot-1.3.3_cs-e9302/include/asm-arm/arch-ep93xx/ep93xx.h --- u-boot-1.3.3/include/asm-arm/arch-ep93xx/ep93xx.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/include/asm-arm/arch-ep93xx/ep93xx.h 2008-06-13 10:41:55.000000000 +0200 @@ -0,0 +1,843 @@ +/* ----------------------------------------------------------------------------- + * Cirrus Logic EP93xx register definitions. + * + * Copyright (C) 2006 + * Dominic Rath + * + * Copyright (C) 2004, 2005 + * Cory T. Tusar, Videon Central, Inc., + * + * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is + * + * Copyright (C) 2004 Ray Lehtiniemi + * Copyright (C) 2003 Cirrus Logic, Inc + * Copyright (C) 1999 ARM Limited. + * + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASSEMBLY__ +#define ep93xx_reg32(x) (*(volatile unsigned long *)(x)) +#define ep93xx_reg16(x) (*(volatile unsigned short *)(x)) +#define ep93xx_reg8(x) (*(volatile unsigned char *)(x)) +#else +#define ep93xx_reg32(x) (x) +#define ep93xx_reg16(x) (x) +#define ep93xx_reg8(x) (x) +#endif + +#define EP93XX_AHB_BASE (0x80000000) +#define EP93XX_APB_BASE (0x80800000) + +/* ----------------------------------------------------------------------------- + * 0x80000000 - 0x8000FFFF: DMA + */ +#define DMA_OFFSET (0x000000) +#define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET) + +#define DMAMP_TX_0_CONTROL ep93xx_reg32(DMA_BASE + 0x0000) +#define DMAMP_TX_0_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0004) +#define DMAMP_TX_0_PPALLOC ep93xx_reg32(DMA_BASE + 0x0008) +#define DMAMP_TX_0_STATUS ep93xx_reg32(DMA_BASE + 0x000C) +#define DMAMP_TX_0_REMAIN ep93xx_reg32(DMA_BASE + 0x0014) +#define DMAMP_TX_0_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x0020) +#define DMAMP_TX_0_BASE0 ep93xx_reg32(DMA_BASE + 0x0024) +#define DMAMP_TX_0_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0028) +#define DMAMP_TX_0_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x0030) +#define DMAMP_TX_0_BASE1 ep93xx_reg32(DMA_BASE + 0x0034) +#define DMAMP_TX_0_CURRENT1 ep93xx_reg32(DMA_BASE + 0x0038) + +#define DMAMP_RX_1_CONTROL ep93xx_reg32(DMA_BASE + 0x0040) +#define DMAMP_RX_1_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0044) +#define DMAMP_RX_1_PPALLOC ep93xx_reg32(DMA_BASE + 0x0048) +#define DMAMP_RX_1_STATUS ep93xx_reg32(DMA_BASE + 0x004C) +#define DMAMP_RX_1_REMAIN ep93xx_reg32(DMA_BASE + 0x0054) +#define DMAMP_RX_1_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x0060) +#define DMAMP_RX_1_BASE0 ep93xx_reg32(DMA_BASE + 0x0064) +#define DMAMP_RX_1_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0068) +#define DMAMP_RX_1_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x0070) +#define DMAMP_RX_1_BASE1 ep93xx_reg32(DMA_BASE + 0x0074) +#define DMAMP_RX_1_CURRENT1 ep93xx_reg32(DMA_BASE + 0x0078) + +#define DMAMP_TX_2_CONTROL ep93xx_reg32(DMA_BASE + 0x0080) +#define DMAMP_TX_2_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0084) +#define DMAMP_TX_2_PPALLOC ep93xx_reg32(DMA_BASE + 0x0088) +#define DMAMP_TX_2_STATUS ep93xx_reg32(DMA_BASE + 0x008C) +#define DMAMP_TX_2_REMAIN ep93xx_reg32(DMA_BASE + 0x0094) +#define DMAMP_TX_2_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x00A0) +#define DMAMP_TX_2_BASE0 ep93xx_reg32(DMA_BASE + 0x00A4) +#define DMAMP_TX_2_CURRENT0 ep93xx_reg32(DMA_BASE + 0x00A8) +#define DMAMP_TX_2_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x00B0) +#define DMAMP_TX_2_BASE1 ep93xx_reg32(DMA_BASE + 0x00B4) +#define DMAMP_TX_2_CURRENT1 ep93xx_reg32(DMA_BASE + 0x00B8) + +#define DMAMP_RX_3_CONTROL ep93xx_reg32(DMA_BASE + 0x00C0) +#define DMAMP_RX_3_INTERRUPT ep93xx_reg32(DMA_BASE + 0x00C4) +#define DMAMP_RX_3_PPALLOC ep93xx_reg32(DMA_BASE + 0x00C8) +#define DMAMP_RX_3_STATUS ep93xx_reg32(DMA_BASE + 0x00CC) +#define DMAMP_RX_3_REMAIN ep93xx_reg32(DMA_BASE + 0x00D4) +#define DMAMP_RX_3_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x00E0) +#define DMAMP_RX_3_BASE0 ep93xx_reg32(DMA_BASE + 0x00E4) +#define DMAMP_RX_3_CURRENT0 ep93xx_reg32(DMA_BASE + 0x00E8) +#define DMAMP_RX_3_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x00F0) +#define DMAMP_RX_3_BASE1 ep93xx_reg32(DMA_BASE + 0x00F4) +#define DMAMP_RX_3_CURRENT1 ep93xx_reg32(DMA_BASE + 0x00F8) + +#define DMAMM_0_CONTROL ep93xx_reg32(DMA_BASE + 0x0100) +#define DMAMM_0_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0104) +#define DMAMM_0_STATUS ep93xx_reg32(DMA_BASE + 0x010C) +#define DMAMM_0_BCR0 ep93xx_reg32(DMA_BASE + 0x0110) +#define DMAMM_0_BCR1 ep93xx_reg32(DMA_BASE + 0x0114) +#define DMAMM_0_SAR_BASE0 ep93xx_reg32(DMA_BASE + 0x0118) +#define DMAMM_0_SAR_BASE1 ep93xx_reg32(DMA_BASE + 0x011C) +#define DMAMM_0_SAR_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0124) +#define DMAMM_0_SAR_CURRENT1 ep93xx_reg32(DMA_BASE + 0x0128) +#define DMAMM_0_DAR_BASE0 ep93xx_reg32(DMA_BASE + 0x012C) +#define DMAMM_0_DAR_BASE1 ep93xx_reg32(DMA_BASE + 0x0130) +#define DMAMM_0_DAR_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0134) +#define DMAMM_0_DAR_CURRENT1 ep93xx_reg32(DMA_BASE + 0x013C) + +#define DMAMM_1_CONTROL ep93xx_reg32(DMA_BASE + 0x0140) +#define DMAMM_1_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0144) +#define DMAMM_1_STATUS ep93xx_reg32(DMA_BASE + 0x014C) +#define DMAMM_1_BCR0 ep93xx_reg32(DMA_BASE + 0x0150) +#define DMAMM_1_BCR1 ep93xx_reg32(DMA_BASE + 0x0154) +#define DMAMM_1_SAR_BASE0 ep93xx_reg32(DMA_BASE + 0x0158) +#define DMAMM_1_SAR_BASE1 ep93xx_reg32(DMA_BASE + 0x015C) +#define DMAMM_1_SAR_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0164) +#define DMAMM_1_SAR_CURRENT1 ep93xx_reg32(DMA_BASE + 0x0168) +#define DMAMM_1_DAR_BASE0 ep93xx_reg32(DMA_BASE + 0x016C) +#define DMAMM_1_DAR_BASE1 ep93xx_reg32(DMA_BASE + 0x0170) +#define DMAMM_1_DAR_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0174) +#define DMAMM_1_DAR_CURRENT1 ep93xx_reg32(DMA_BASE + 0x017C) + +#define DMAMP_RX_5_CONTROL ep93xx_reg32(DMA_BASE + 0x0200) +#define DMAMP_RX_5_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0204) +#define DMAMP_RX_5_PPALLOC ep93xx_reg32(DMA_BASE + 0x0208) +#define DMAMP_RX_5_STATUS ep93xx_reg32(DMA_BASE + 0x020C) +#define DMAMP_RX_5_REMAIN ep93xx_reg32(DMA_BASE + 0x0214) +#define DMAMP_RX_5_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x0220) +#define DMAMP_RX_5_BASE0 ep93xx_reg32(DMA_BASE + 0x0224) +#define DMAMP_RX_5_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0228) +#define DMAMP_RX_5_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x0230) +#define DMAMP_RX_5_BASE1 ep93xx_reg32(DMA_BASE + 0x0234) +#define DMAMP_RX_5_CURRENT1 ep93xx_reg32(DMA_BASE + 0x0238) + +#define DMAMP_TX_4_CONTROL ep93xx_reg32(DMA_BASE + 0x0240) +#define DMAMP_TX_4_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0244) +#define DMAMP_TX_4_PPALLOC ep93xx_reg32(DMA_BASE + 0x0248) +#define DMAMP_TX_4_STATUS ep93xx_reg32(DMA_BASE + 0x024C) +#define DMAMP_TX_4_REMAIN ep93xx_reg32(DMA_BASE + 0x0254) +#define DMAMP_TX_4_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x0260) +#define DMAMP_TX_4_BASE0 ep93xx_reg32(DMA_BASE + 0x0264) +#define DMAMP_TX_4_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0268) +#define DMAMP_TX_4_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x0270) +#define DMAMP_TX_4_BASE1 ep93xx_reg32(DMA_BASE + 0x0274) +#define DMAMP_TX_4_CURRENT1 ep93xx_reg32(DMA_BASE + 0x0278) + +#define DMAMP_RX_7_CONTROL ep93xx_reg32(DMA_BASE + 0x0280) +#define DMAMP_RX_7_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0284) +#define DMAMP_RX_7_PPALLOC ep93xx_reg32(DMA_BASE + 0x0288) +#define DMAMP_RX_7_STATUS ep93xx_reg32(DMA_BASE + 0x028C) +#define DMAMP_RX_7_REMAIN ep93xx_reg32(DMA_BASE + 0x0294) +#define DMAMP_RX_7_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x02A0) +#define DMAMP_RX_7_BASE0 ep93xx_reg32(DMA_BASE + 0x02A4) +#define DMAMP_RX_7_CURRENT0 ep93xx_reg32(DMA_BASE + 0x02A8) +#define DMAMP_RX_7_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x02B0) +#define DMAMP_RX_7_BASE1 ep93xx_reg32(DMA_BASE + 0x02B4) +#define DMAMP_RX_7_CURRENT1 ep93xx_reg32(DMA_BASE + 0x02B8) + +#define DMAMP_TX_6_CONTROL ep93xx_reg32(DMA_BASE + 0x02C0) +#define DMAMP_TX_6_INTERRUPT ep93xx_reg32(DMA_BASE + 0x02C4) +#define DMAMP_TX_6_PPALLOC ep93xx_reg32(DMA_BASE + 0x02C8) +#define DMAMP_TX_6_STATUS ep93xx_reg32(DMA_BASE + 0x02CC) +#define DMAMP_TX_6_REMAIN ep93xx_reg32(DMA_BASE + 0x02D4) +#define DMAMP_TX_6_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x02E0) +#define DMAMP_TX_6_BASE0 ep93xx_reg32(DMA_BASE + 0x02E4) +#define DMAMP_TX_6_CURRENT0 ep93xx_reg32(DMA_BASE + 0x02E8) +#define DMAMP_TX_6_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x02F0) +#define DMAMP_TX_6_BASE1 ep93xx_reg32(DMA_BASE + 0x02F4) +#define DMAMP_TX_6_CURRENT1 ep93xx_reg32(DMA_BASE + 0x02F8) + +#define DMAMP_RX_9_CONTROL ep93xx_reg32(DMA_BASE + 0x0300) +#define DMAMP_RX_9_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0304) +#define DMAMP_RX_9_PPALLOC ep93xx_reg32(DMA_BASE + 0x0308) +#define DMAMP_RX_9_STATUS ep93xx_reg32(DMA_BASE + 0x030C) +#define DMAMP_RX_9_REMAIN ep93xx_reg32(DMA_BASE + 0x0314) +#define DMAMP_RX_9_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x0320) +#define DMAMP_RX_9_BASE0 ep93xx_reg32(DMA_BASE + 0x0324) +#define DMAMP_RX_9_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0328) +#define DMAMP_RX_9_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x0330) +#define DMAMP_RX_9_BASE1 ep93xx_reg32(DMA_BASE + 0x0334) +#define DMAMP_RX_9_CURRENT1 ep93xx_reg32(DMA_BASE + 0x0338) + +#define DMAMP_TX_8_CONTROL ep93xx_reg32(DMA_BASE + 0x0340) +#define DMAMP_TX_8_INTERRUPT ep93xx_reg32(DMA_BASE + 0x0344) +#define DMAMP_TX_8_PPALLOC ep93xx_reg32(DMA_BASE + 0x0348) +#define DMAMP_TX_8_STATUS ep93xx_reg32(DMA_BASE + 0x034C) +#define DMAMP_TX_8_REMAIN ep93xx_reg32(DMA_BASE + 0x0354) +#define DMAMP_TX_8_MAXCNT0 ep93xx_reg32(DMA_BASE + 0x0360) +#define DMAMP_TX_8_BASE0 ep93xx_reg32(DMA_BASE + 0x0364) +#define DMAMP_TX_8_CURRENT0 ep93xx_reg32(DMA_BASE + 0x0368) +#define DMAMP_TX_8_MAXCNT1 ep93xx_reg32(DMA_BASE + 0x0370) +#define DMAMP_TX_8_BASE1 ep93xx_reg32(DMA_BASE + 0x0374) +#define DMAMP_TX_8_CURRENT1 ep93xx_reg32(DMA_BASE + 0x0378) + +#define DMA_ARBITRATION ep93xx_reg32(DMA_BASE + 0x0380) +#define DMA_INTERRUPT ep93xx_reg32(DMA_BASE + 0x03C0) + + +/* ----------------------------------------------------------------------------- + * 0x80010000 - 0x8001FFFF: Ethernet MAC + */ +#define MAC_OFFSET (0x010000) +#define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET) + +#define MAC_RXCTL ep93xx_reg32(MAC_BASE + 0x0000) +#define MAC_TXCTL ep93xx_reg32(MAC_BASE + 0x0004) +#define MAC_TESTCTL ep93xx_reg32(MAC_BASE + 0x0008) +#define MAC_MIICMD ep93xx_reg32(MAC_BASE + 0x0010) +#define MAC_MIIDATA ep93xx_reg32(MAC_BASE + 0x0014) +#define MAC_MIISTS ep93xx_reg32(MAC_BASE + 0x0018) +#define MAC_SELFCTL ep93xx_reg32(MAC_BASE + 0x0020) +#define MAC_INTEN ep93xx_reg32(MAC_BASE + 0x0024) +#define MAC_INTSTSP ep93xx_reg32(MAC_BASE + 0x0028) +#define MAC_INTSTSC ep93xx_reg32(MAC_BASE + 0x002C) +#define MAC_DIAGAD ep93xx_reg32(MAC_BASE + 0x0038) +#define MAC_DIAGDATA ep93xx_reg32(MAC_BASE + 0x003C) +#define MAC_GT ep93xx_reg32(MAC_BASE + 0x0040) +#define MAC_FCT ep93xx_reg32(MAC_BASE + 0x0044) +#define MAC_FCF ep93xx_reg32(MAC_BASE + 0x0048) +#define MAC_AFP ep93xx_reg32(MAC_BASE + 0x004C) +#define MAC_HASHTBL ep93xx_reg32(MAC_BASE + 0x0050) +#define MAC_INDAD ep93xx_reg32(MAC_BASE + 0x0050) +#define MAC_INDAD_UPPER ep93xx_reg32(MAC_BASE + 0x0054) +#define MAC_GIINTSTS ep93xx_reg32(MAC_BASE + 0x0060) +#define MAC_GIINTMSK ep93xx_reg32(MAC_BASE + 0x0064) +#define MAC_GIINTROSTS ep93xx_reg32(MAC_BASE + 0x0068) +#define MAC_GIINTFRC ep93xx_reg32(MAC_BASE + 0x006C) +#define MAC_TXCOLLCNT ep93xx_reg32(MAC_BASE + 0x0070) +#define MAC_RXMISSCNT ep93xx_reg32(MAC_BASE + 0x0074) +#define MAC_RXRUNTCNT ep93xx_reg32(MAC_BASE + 0x0078) +#define MAC_BMCTL ep93xx_reg32(MAC_BASE + 0x0080) +#define MAC_BMSTS ep93xx_reg32(MAC_BASE + 0x0084) +#define MAC_RXBCA ep93xx_reg32(MAC_BASE + 0x0088) +#define MAC_RXDQBADD ep93xx_reg32(MAC_BASE + 0x0090) +#define MAC_RXDQBLEN ep93xx_reg16(MAC_BASE + 0x0094) +#define MAC_RXDQCURLEN ep93xx_reg16(MAC_BASE + 0x0096) +#define MAC_RXDQCURADD ep93xx_reg32(MAC_BASE + 0x0098) +#define MAC_RXDENQ ep93xx_reg32(MAC_BASE + 0x009C) +#define MAC_RXSTSQBADD ep93xx_reg32(MAC_BASE + 0x00A0) +#define MAC_RXSTSQBLEN ep93xx_reg16(MAC_BASE + 0x00A4) +#define MAC_RXSTSQCURLEN ep93xx_reg16(MAC_BASE + 0x00A6) +#define MAC_RXSTSQCURADD ep93xx_reg32(MAC_BASE + 0x00A8) +#define MAC_RXSTSENQ ep93xx_reg32(MAC_BASE + 0x00AC) +#define MAC_TXDQBADD ep93xx_reg32(MAC_BASE + 0x00B0) +#define MAC_TXDQBLEN ep93xx_reg32(MAC_BASE + 0x00B4) +#define MAC_TXDQCURLEN ep93xx_reg32(MAC_BASE + 0x00B6) +#define MAC_TXDQCURADD ep93xx_reg32(MAC_BASE + 0x00B8) +#define MAC_TXDENQ ep93xx_reg32(MAC_BASE + 0x00BC) +#define MAC_TXSTSQBADD ep93xx_reg32(MAC_BASE + 0x00C0) +#define MAC_TXSTSQBLEN ep93xx_reg32(MAC_BASE + 0x00C4) +#define MAC_TXSTSQCURLEN ep93xx_reg32(MAC_BASE + 0x00C6) +#define MAC_TXSTSQCURADD ep93xx_reg32(MAC_BASE + 0x00C8) +#define MAC_RXBUFTHRSHLD ep93xx_reg32(MAC_BASE + 0x00D0) +#define MAC_TXBUFTHRSHLD ep93xx_reg32(MAC_BASE + 0x00D4) +#define MAC_RXSTSTHRSHLD ep93xx_reg32(MAC_BASE + 0x00D8) +#define MAC_TXSTSTHRSHLD ep93xx_reg32(MAC_BASE + 0x00DC) +#define MAC_RXDTHRSHLD ep93xx_reg32(MAC_BASE + 0x00E0) +#define MAC_TXDTHRSHLD ep93xx_reg32(MAC_BASE + 0x00E4) +#define MAC_MAXFRMLEN ep93xx_reg32(MAC_BASE + 0x00E8) +#define MAC_RXHDRLEN ep93xx_reg32(MAC_BASE + 0x00EC) + +#define SELFCTL_RWP (1<<0x07) +#define SELFCTL_GPO0 (1<<0x05) +#define SELFCTL_PUWE (1<<0x04) +#define SELFCTL_PDWE (1<<0x03) +#define SELFCTL_MIIL (1<<0x02) +#define SELFCTL_RESET (1<<0x00) + +#define INTSTS_RWI (1L<<0x1e) +#define INTSTS_RXMI (1L<<0x1d) +#define INTSTS_RXBI (1L<<0x1c) +#define INTSTS_RXSQI (1L<<0x1b) +#define INTSTS_TXLEI (1L<<0x1a) +#define INTSTS_ECIE (1L<<0x19) +#define INTSTS_TXUHI (1L<<0x18) +#define INTSTS_MOI (1L<<0x12) +#define INTSTS_TXCOI (1L<<0x11) +#define INTSTS_RXROI (1L<<0x10) +#define INTSTS_MIII (1L<<0x0c) +#define INTSTS_PHYI (1L<<0x0b) +#define INTSTS_TI (1L<<0x0a) +#define INTSTS_AHBE (1L<<0x08) +#define INTSTS_OTHER (1L<<0x04) +#define INTSTS_TXSQ (1L<<0x03) +#define INTSTS_RXSQ (1L<<0x02) + +#define BMCTL_MT (1<<0x0d) +#define BMCTL_TT (1<<0x0c) +#define BMCTL_UNH (1<<0x0b) +#define BMCTL_TXCHR (1<<0x0a) +#define BMCTL_TXDIS (1<<0x09) +#define BMCTL_TXEN (1<<0x08) +#define BMCTL_EH2 (1<<0x06) +#define BMCTL_EH1 (1<<0x05) +#define BMCTL_EEOB (1<<0x04) +#define BMCTL_RXCHR (1<<0x02) +#define BMCTL_RXDIS (1<<0x01) +#define BMCTL_RXEN (1<<0x00) + +#define BMSTS_TXACT (1<<0x07) +#define BMSTS_TP (1<<0x04) +#define BMSTS_RXACT (1<<0x03) +#define BMSTS_QID_MASK (0x07) +#define BMSTS_QID_RXDATA (0x00) +#define BMSTS_QID_TXDATA (0x01) +#define BMSTS_QID_RXSTS (0x02) +#define BMSTS_QID_TXSTS (0x03) +#define BMSTS_QID_RXDESC (0x04) +#define BMSTS_QID_TXDESC (0x05) + +#define AFP_MASK (0x07) +#define AFP_IAPRIMARY (0x00) +#define AFP_IASECONDARY1 (0x01) +#define AFP_IASECONDARY2 (0x02) +#define AFP_IASECONDARY3 (0x03) +#define AFP_TX (0x06) +#define AFP_HASH (0x07) + +#define RXCTL_PAUSEA (1l<<0x14) +#define RXCTL_RXFCE1 (1l<<0x13) +#define RXCTL_RXFCE0 (1l<<0x12) +#define RXCTL_BCRC (1l<<0x11) +#define RXCTL_SRXON (1l<<0x10) +#define RXCTL_RCRCA (1l<<0x0d) +#define RXCTL_RA (1l<<0x0c) +#define RXCTL_PA (1l<<0x0b) +#define RXCTL_BA (1l<<0x0a) +#define RXCTL_MA (1l<<0x09) +#define RXCTL_IAHA (1l<<0x08) +#define RXCTL_IA3 (1l<<0x03) +#define RXCTL_IA2 (1l<<0x02) +#define RXCTL_IA1 (1l<<0x01) +#define RXCTL_IA0 (1l<<0x00) + +#define TXCTL_DEFDIS (1<<0x07) +#define TXCTL_MBE (1<<0x06) +#define TXCTL_ICRC (1<<0x05) +#define TXCTL_TPD (1<<0x04) +#define TXCTL_OCOLL (1<<0x03) +#define TXCTL_SP (1<<0x02) +#define TXCTL_PB (1<<0x01) +#define TXCTL_STXON (1<<0x00) + +#define MIICMD_REGAD_MASK (0x001F) +#define MIICMD_PHYAD_MASK (0x03E0) +#define MIICMD_OPCODE_MASK (0xC000) +#define MIICMD_PHYAD_8950 (0x0000) +#define MIICMD_OPCODE_READ (0x8000) +#define MIICMD_OPCODE_WRITE (0x4000) + +#define MIISTS_BUSY (1<<0x00) + +/* ----------------------------------------------------------------------------- + * 0x80020000 - 0x8002FFFF: USB OHCI + */ +#define USB_OFFSET (0x020000) +#define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET) + +#define USB_HCREVISION ep93xx_reg32(USB_BASE + 0x0000) +#define USB_HCCONTROL ep93xx_reg32(USB_BASE + 0x0004) +#define USB_HCCOMMANDSTATUS ep93xx_reg32(USB_BASE + 0x0008) +#define USB_HCINTERRUPTSTATUS ep93xx_reg32(USB_BASE + 0x000C) +#define USB_HCINTERRUPTENABLE ep93xx_reg32(USB_BASE + 0x0010) +#define USB_HCINTERRUPTDISABLE ep93xx_reg32(USB_BASE + 0x0014) +#define USB_HCHCCA ep93xx_reg32(USB_BASE + 0x0018) +#define USB_HCPERIODCURRENTED ep93xx_reg32(USB_BASE + 0x001C) +#define USB_HCCONTROLHEADED ep93xx_reg32(USB_BASE + 0x0020) +#define USB_HCCONTROLCURRENTED ep93xx_reg32(USB_BASE + 0x0024) +#define USB_HCBULKHEADED ep93xx_reg32(USB_BASE + 0x0028) +#define USB_HCBULKCURRENTED ep93xx_reg32(USB_BASE + 0x002C) +#define USB_HCDONEHEAD ep93xx_reg32(USB_BASE + 0x0030) +#define USB_HCFMINTERVAL ep93xx_reg32(USB_BASE + 0x0034) +#define USB_HCFMREMAINING ep93xx_reg32(USB_BASE + 0x0038) +#define USB_HCFMNUMBER ep93xx_reg32(USB_BASE + 0x003C) +#define USB_HCPERIODICSTART ep93xx_reg32(USB_BASE + 0x0040) +#define USB_HCLSTHRESHOLD ep93xx_reg32(USB_BASE + 0x0044) +#define USB_HCRHDESCRIPTORA ep93xx_reg32(USB_BASE + 0x0048) +#define USB_HCRHDESCRIPTORB ep93xx_reg32(USB_BASE + 0x004C) +#define USB_HCRHSTATUS ep93xx_reg32(USB_BASE + 0x0050) +#define USB_HCRHPORTSTATUS0 ep93xx_reg32(USB_BASE + 0x0054) +#if (defined(EP9302) || defined(EP9307) || defined(EP9312) || defined(EP9315)) +#define USB_HCRHPORTSTATUS1 ep93xx_reg32(USB_BASE + 0x0058) +#endif +#define USB_HCRHPORTSTATUS2 ep93xx_reg32(USB_BASE + 0x005C) +#define USB_CFGCTRL ep93xx_reg32(USB_BASE + 0x0080) +#define USB_HCISTS ep93xx_reg32(USB_BASE + 0x0084) + + +/* ----------------------------------------------------------------------------- + * 0x80030000 - 0x8003FFFF: Raster engine + */ +#if (defined(EP9307) || defined(EP9312) || defined(EP9315)) +#define RASTER_OFFSET (0x030000) +#define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET) + +#define RASTER_VLINESTOTAL ep93xx_reg32(RASTER_BASE + 0x0000) +#define RASTER_VSYNCSTRTSTOP ep93xx_reg32(RASTER_BASE + 0x0004) +#define RASTER_VACTIVESTRTSTOP ep93xx_reg32(RASTER_BASE + 0x0008) +#define RASTER_VCLKSTRTSTOP ep93xx_reg32(RASTER_BASE + 0x000C) +#define RASTER_HCLKSTOTAL ep93xx_reg32(RASTER_BASE + 0x0010) +#define RASTER_HSYNCSTRTSTOP ep93xx_reg32(RASTER_BASE + 0x0014) +#define RASTER_HACTIVESTRTSTOP ep93xx_reg32(RASTER_BASE + 0x0018) +#define RASTER_HCLKSTRTSTOP ep93xx_reg32(RASTER_BASE + 0x001C) +#define RASTER_BRIGHTNESS ep93xx_reg32(RASTER_BASE + 0x0020) +#define RASTER_VIDEOATTRIBS ep93xx_reg32(RASTER_BASE + 0x0024) +#define RASTER_VIDSCRNPAGE ep93xx_reg32(RASTER_BASE + 0x0028) +#define RASTER_VIDSCRNHPG ep93xx_reg32(RASTER_BASE + 0x002C) +#define RASTER_SCRNLINES ep93xx_reg32(RASTER_BASE + 0x0030) +#define RASTER_LINELENGTH ep93xx_reg32(RASTER_BASE + 0x0034) +#define RASTER_VLINESTEP ep93xx_reg32(RASTER_BASE + 0x0038) +#define RASTER_LINECARRY ep93xx_reg32(RASTER_BASE + 0x003C) +#define RASTER_BLINKRATE ep93xx_reg32(RASTER_BASE + 0x0040) +#define RASTER_BLINKMASK ep93xx_reg32(RASTER_BASE + 0x0044) +#define RASTER_BLINKPATTRN ep93xx_reg32(RASTER_BASE + 0x0048) +#define RASTER_PATTRNMASK ep93xx_reg32(RASTER_BASE + 0x004C) +#define RASTER_BG_OFFSET ep93xx_reg32(RASTER_BASE + 0x0050) +#define RASTER_PIXELMODE ep93xx_reg32(RASTER_BASE + 0x0054) +#define RASTER_PARLLIFOUT ep93xx_reg32(RASTER_BASE + 0x0058) +#define RASTER_PARLLIFIN ep93xx_reg32(RASTER_BASE + 0x005C) +#define RASTER_CURSOR_ADR_START ep93xx_reg32(RASTER_BASE + 0x0060) +#define RASTER_CURSOR_ADR_RESET ep93xx_reg32(RASTER_BASE + 0x0064) +#define RASTER_CURSORSIZE ep93xx_reg32(RASTER_BASE + 0x0068) +#define RASTER_CURSORCOLOR1 ep93xx_reg32(RASTER_BASE + 0x006C) +#define RASTER_CURSORCOLOR2 ep93xx_reg32(RASTER_BASE + 0x0070) +#define RASTER_CURSORXYLOC ep93xx_reg32(RASTER_BASE + 0x0074) +#define RASTER_CURSOR_DHSCAN_LH_YLOC ep93xx_reg32(RASTER_BASE + 0x0078) +#define RASTER_REALITI_SWLOCK ep93xx_reg32(RASTER_BASE + 0x007C) +#define RASTER_GS_LUT ep93xx_reg32(RASTER_BASE + 0x0080) +#define RASTER_REALITI_TCR ep93xx_reg32(RASTER_BASE + 0x0100) +#define RASTER_REALITI_TISRA ep93xx_reg32(RASTER_BASE + 0x0104) +#define RASTER_REALITI_TISRB ep93xx_reg32(RASTER_BASE + 0x0108) +#define RASTER_CURSOR_TISR ep93xx_reg32(RASTER_BASE + 0x010C) +#define RASTER_REALITI_TOCRA ep93xx_reg32(RASTER_BASE + 0x0110) +#define RASTER_REALITI_TOCRB ep93xx_reg32(RASTER_BASE + 0x0114) +#define RASTER_FIFO_TOCRA ep93xx_reg32(RASTER_BASE + 0x0118) +#define RASTER_FIFO_TOCRB ep93xx_reg32(RASTER_BASE + 0x011C) +#define RASTER_BLINK_TISR ep93xx_reg32(RASTER_BASE + 0x0120) +#define RASTER_DAC_TISRA ep93xx_reg32(RASTER_BASE + 0x0124) +#define RASTER_DAC_TISRB ep93xx_reg32(RASTER_BASE + 0x0128) +#define RASTER_SHIFT_TISR ep93xx_reg32(RASTER_BASE + 0x012C) +#define RASTER_DACMUX_TOCRA ep93xx_reg32(RASTER_BASE + 0x0130) +#define RASTER_DACMUX_TOCRB ep93xx_reg32(RASTER_BASE + 0x0134) +#define RASTER_PELMUX_TOCR ep93xx_reg32(RASTER_BASE + 0x0138) +#define RASTER_VIDEO_TOCRA ep93xx_reg32(RASTER_BASE + 0x013C) +#define RASTER_VIDEO_TOCRB ep93xx_reg32(RASTER_BASE + 0x0140) +#define RASTER_YCRCB_TOCR ep93xx_reg32(RASTER_BASE + 0x0144) +#define RASTER_CURSOR_TOCR ep93xx_reg32(RASTER_BASE + 0x0148) +#define RASTER_VIDEO_TOCRC ep93xx_reg32(RASTER_BASE + 0x014C) +#define RASTER_SHIFT_TOCR ep93xx_reg32(RASTER_BASE + 0x0150) +#define RASTER_BLINK_TOCR ep93xx_reg32(RASTER_BASE + 0x0154) +#define RASTER_REALITI_TCER ep93xx_reg32(RASTER_BASE + 0x0180) +#define RASTER_SIGVAL ep93xx_reg32(RASTER_BASE + 0x0200) +#define RASTER_SIGCTL ep93xx_reg32(RASTER_BASE + 0x0204) +#define RASTER_VSIGSTRTSTOP ep93xx_reg32(RASTER_BASE + 0x0208) +#define RASTER_HSIGSTRTSTOP ep93xx_reg32(RASTER_BASE + 0x020C) +#define RASTER_SIGCLR ep93xx_reg32(RASTER_BASE + 0x0210) +#define RASTER_ACRATE ep93xx_reg32(RASTER_BASE + 0x0214) +#define RASTER_LUTCONT ep93xx_reg32(RASTER_BASE + 0x0218) +#define RASTER_VBLANKSTRTSTOP ep93xx_reg32(RASTER_BASE + 0x0228) +#define RASTER_HBLANKSTRTSTOP ep93xx_reg32(RASTER_BASE + 0x022C) +#define RASTER_LUT ep93xx_reg32(RASTER_BASE + 0x0400) +#define RASTER_CURSORBLINK1 ep93xx_reg32(RASTER_BASE + 0x021C) +#define RASTER_CURSORBLINK2 ep93xx_reg32(RASTER_BASE + 0x0220) +#define RASTER_CURSORBLINK ep93xx_reg32(RASTER_BASE + 0x0224) +#define RASTER_EOLOFFSET ep93xx_reg32(RASTER_BASE + 0x0230) +#define RASTER_FIFOLEVEL ep93xx_reg32(RASTER_BASE + 0x0234) +#define RASTER_GS_LUT2 ep93xx_reg32(RASTER_BASE + 0x0280) +#define RASTER_GS_LUT3 ep93xx_reg32(RASTER_BASE + 0x0300) +#define RASTER_COLOR_LUT ep93xx_reg32(RASTER_BASE + 0x0400) +#endif + + +/* ----------------------------------------------------------------------------- + * 0x80040000 - 0x8004FFFF: Graphics accelerator + */ +#if defined(EP9315) +#define GFX_OFFSET (0x040000) +#define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET) +#endif + + +/* ----------------------------------------------------------------------------- + * 0x80050000 - 0x8005FFFF: Reserved + */ + + +/* ----------------------------------------------------------------------------- + * 0x80060000 - 0x8006FFFF: SDRAM controller + */ +#define SDRAM_OFFSET (0x060000) +#define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET) + +#define SDRAM_GLCONFIG ep93xx_reg32(SDRAM_BASE + 0x0004) +#define SDRAM_REFRSHTIMR ep93xx_reg32(SDRAM_BASE + 0x0008) +#define SDRAM_BOOTSTS ep93xx_reg32(SDRAM_BASE + 0x000C) +#define SDRAM_DEVCFG0 ep93xx_reg32(SDRAM_BASE + 0x0010) +#define SDRAM_DEVCFG1 ep93xx_reg32(SDRAM_BASE + 0x0014) +#define SDRAM_DEVCFG2 ep93xx_reg32(SDRAM_BASE + 0x0018) +#define SDRAM_DEVCFG3 ep93xx_reg32(SDRAM_BASE + 0x001C) + +#define GLOBALCFG_INIT 0x00000001 +#define GLOBALCFG_MRS 0x00000002 +#define GLOBALCFG_SMEMBUSY 0x00000020 +#define GLOBALCFG_LCR 0x00000040 +#define GLOBALCFG_REARBEN 0x00000080 +#define GLOBALCFG_CLKSHUTDOWN 0x40000000 +#define GLOBALCFG_CKE 0x80000000 + + +/* ----------------------------------------------------------------------------- + * 0x80070000 - 0x8007FFFF: Reserved + */ + + +/* ----------------------------------------------------------------------------- + * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA + */ +#define SMC_OFFSET (0x080000) +#define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET) + +#define SMC_BCR0 ep93xx_reg32(SMC_BASE + 0x0000) +#define SMC_BCR1 ep93xx_reg32(SMC_BASE + 0x0004) +#define SMC_BCR2 ep93xx_reg32(SMC_BASE + 0x0008) +#define SMC_BCR3 ep93xx_reg32(SMC_BASE + 0x000C) +#define SMC_BCR6 ep93xx_reg32(SMC_BASE + 0x0018) +#define SMC_BCR7 ep93xx_reg32(SMC_BASE + 0x001C) +#if (defined(EP9307) || defined(EP9315)) +#define SMC_PCATTRIBUTE ep93xx_reg32(SMC_BASE + 0x0020) +#define SMC_PCCOMMON ep93xx_reg32(SMC_BASE + 0x0024) +#define SMC_PCIO ep93xx_reg32(SMC_BASE + 0x0028) +#define SMC_PCMCIACTRL ep93xx_reg32(SMC_BASE + 0x0040) +#endif + + +/* ----------------------------------------------------------------------------- + * 0x80090000 - 0x8009FFFF: Boot ROM + */ + + +/* ----------------------------------------------------------------------------- + * 0x800A0000 - 0x800AFFFF: IDE interface + */ + + +/* ----------------------------------------------------------------------------- + * 0x800B0000 - 0x800BFFFF: VIC1 + */ + + +/* ----------------------------------------------------------------------------- + * 0x800C0000 - 0x800CFFFF: VIC2 + */ + + +/* ----------------------------------------------------------------------------- + * 0x800D0000 - 0x800FFFFF: Reserved + */ + + +/* ----------------------------------------------------------------------------- + * 0x80800000 - 0x8080FFFF: Reserved + */ + + +/* ----------------------------------------------------------------------------- + * 0x80810000 - 0x8081FFFF: Timers + */ +#define TIMER_OFFSET (0x010000) +#define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET) + +#define TIMER1_LOAD ep93xx_reg32(TIMER_BASE + 0x0000) +#define TIMER1_VALUE ep93xx_reg32(TIMER_BASE + 0x0004) +#define TIMER1_CONTROL ep93xx_reg32(TIMER_BASE + 0x0008) +#define TIMER1_CLEAR ep93xx_reg32(TIMER_BASE + 0x000c) + +#define TIMER2_LOAD ep93xx_reg32(TIMER_BASE + 0x0020) +#define TIMER2_VALUE ep93xx_reg32(TIMER_BASE + 0x0024) +#define TIMER2_CONTROL ep93xx_reg32(TIMER_BASE + 0x0028) +#define TIMER2_CLEAR ep93xx_reg32(TIMER_BASE + 0x002c) + +#define TIMER3_LOAD ep93xx_reg32(TIMER_BASE + 0x0080) +#define TIMER3_VALUE ep93xx_reg32(TIMER_BASE + 0x0084) +#define TIMER3_CONTROL ep93xx_reg32(TIMER_BASE + 0x0088) +#define TIMER3_CLEAR ep93xx_reg32(TIMER_BASE + 0x008c) + + +/* ----------------------------------------------------------------------------- + * 0x80820000 - 0x8082FFFF: I2S + */ +#define I2S_OFFSET (0x020000) +#define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET) + + +/* ----------------------------------------------------------------------------- + * 0x80830000 - 0x8083FFFF: Security + */ +#define SECURITY_OFFSET (0x030000) +#define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET) + +#define EXTENSIONID ep93xx_reg32(SECURITY_BASE + 0x2714) + + +/* ----------------------------------------------------------------------------- + * 0x80840000 - 0x8084FFFF: GPIO + */ +#define GPIO_OFFSET (0x040000) +#define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET) + +#define GPIO_PADR ep93xx_reg16(GPIO_BASE + 0x0000) +#define GPIO_PBDR ep93xx_reg16(GPIO_BASE + 0x0004) +#define GPIO_PCDR ep93xx_reg16(GPIO_BASE + 0x0008) +#define GPIO_PDDR ep93xx_reg16(GPIO_BASE + 0x000c) + +#define GPIO_PADDR ep93xx_reg16(GPIO_BASE + 0x0010) +#define GPIO_PBDDR ep93xx_reg16(GPIO_BASE + 0x0014) +#define GPIO_PCDDR ep93xx_reg16(GPIO_BASE + 0x0018) +#define GPIO_PDDDR ep93xx_reg16(GPIO_BASE + 0x001c) + +#define GPIO_PEDR ep93xx_reg16(GPIO_BASE + 0x0020) +#define GPIO_PEDDR ep93xx_reg16(GPIO_BASE + 0x0024) +#define GPIO_PFDR ep93xx_reg16(GPIO_BASE + 0x0030) +#define GPIO_PFDDR ep93xx_reg16(GPIO_BASE + 0x0034) +#define GPIO_PGDR ep93xx_reg16(GPIO_BASE + 0x0038) +#define GPIO_PGDDR ep93xx_reg16(GPIO_BASE + 0x003c) +#define GPIO_PHDR ep93xx_reg16(GPIO_BASE + 0x0040) +#define GPIO_PHDDR ep93xx_reg16(GPIO_BASE + 0x0044) + +#define GPIO_FINTTYPE1 ep93xx_reg16(GPIO_BASE + 0x004c) +#define GPIO_FINTTYPE2 ep93xx_reg16(GPIO_BASE + 0x0050) +#define GPIO_FEOI ep93xx_reg16(GPIO_BASE + 0x0054) +#define GPIO_FINTEN ep93xx_reg16(GPIO_BASE + 0x0058) +#define GPIO_INTSTSF ep93xx_reg16(GPIO_BASE + 0x005c) +#define GPIO_RAWINTSTSF ep93xx_reg16(GPIO_BASE + 0x0060) +#define GPIO_FDB ep93xx_reg16(GPIO_BASE + 0x0064) + +#define GPIO_AINTTYPE1 ep93xx_reg16(GPIO_BASE + 0x0090) +#define GPIO_AINTTYPE2 ep93xx_reg16(GPIO_BASE + 0x0094) +#define GPIO_AEOI ep93xx_reg16(GPIO_BASE + 0x0098) +#define GPIO_AINTEN ep93xx_reg16(GPIO_BASE + 0x009c) +#define GPIO_INTSTSA ep93xx_reg16(GPIO_BASE + 0x00a0) +#define GPIO_RAWINTSTSA ep93xx_reg16(GPIO_BASE + 0x00a4) +#define GPIO_ADB ep93xx_reg16(GPIO_BASE + 0x00a8) + +#define GPIO_BINTTYPE1 ep93xx_reg16(GPIO_BASE + 0x00ac) +#define GPIO_BINTTYPE2 ep93xx_reg16(GPIO_BASE + 0x00b0) +#define GPIO_BEOI ep93xx_reg16(GPIO_BASE + 0x00b4) +#define GPIO_BINTEN ep93xx_reg16(GPIO_BASE + 0x00b8) +#define GPIO_INTSTSB ep93xx_reg16(GPIO_BASE + 0x00bc) +#define GPIO_RAWINTSTSB ep93xx_reg16(GPIO_BASE + 0x00c0) +#define GPIO_BDB ep93xx_reg16(GPIO_BASE + 0x00c4) + +#define GPIO_EEDRIVE ep93xx_reg16(GPIO_BASE + 0x00c8) + + +/* ----------------------------------------------------------------------------- + * 0x80850000 - 0x8087FFFF: Reserved + */ + + +/* ----------------------------------------------------------------------------- + * 0x80880000 - 0x8088FFFF: AAC + */ +#define AAC_OFFSET (0x080000) +#define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET) + + +/* ----------------------------------------------------------------------------- + * 0x80890000 - 0x8089FFFF: Reserved + */ + + +/* ----------------------------------------------------------------------------- + * 0x808A0000 - 0x808AFFFF: SPI + */ +#define SPI_OFFSET (0x0A0000) +#define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET) + +#define SPI_SSP1CR0 ep93xx_reg16(SPI_BASE + 0x0000) +#define SPI_SSP1CR1 ep93xx_reg16(SPI_BASE + 0x0004) +#define SPI_SSP1DR ep93xx_reg16(SPI_BASE + 0x0008) +#define SPI_SSP1SR ep93xx_reg16(SPI_BASE + 0x000c) +#define SPI_SSP1CPSR ep93xx_reg16(SPI_BASE + 0x0010) +#define SPI_SSP1IIR ep93xx_reg16(SPI_BASE + 0x0014) + + +/* ----------------------------------------------------------------------------- + * 0x808B0000 - 0x808BFFFF: IrDA + */ +#define IRDA_OFFSET (0x0B0000) +#define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET) + + +/* ----------------------------------------------------------------------------- + * 0x808C0000 - 0x808CFFFF: UART1 + */ +#define UART1_OFFSET (0x0C0000) +#define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET) + +#define UART1_DATA ep93xx_reg32(UART1_BASE + 0x0000) +#define UART1_RXSTS ep93xx_reg32(UART1_BASE + 0x0004) +#define UART1_LIN_CTRLHIGH ep93xx_reg32(UART1_BASE + 0x0008) +#define UART1_LIN_CTRLMID ep93xx_reg32(UART1_BASE + 0x000c) +#define UART1_LIN_CTRLLOW ep93xx_reg32(UART1_BASE + 0x0010) +#define UART1_CTRL ep93xx_reg32(UART1_BASE + 0x0014) +#define UART1_FLAG ep93xx_reg32(UART1_BASE + 0x0018) +#define UART1_INTIDINTCLR ep93xx_reg32(UART1_BASE + 0x001c) + +#define UART1_DMA_CTRL ep93xx_reg32(UART1_BASE + 0x0028) + +#define UART1_MODEM_CTRL ep93xx_reg32(UART1_BASE + 0x0100) +#define UART1_MODEM_STS ep93xx_reg32(UART1_BASE + 0x0104) + +#define UART1_HDLC_CTRL ep93xx_reg32(UART1_BASE + 0x020c) +#define UART1_HDLC_ADDMTCHVAL ep93xx_reg32(UART1_BASE + 0x0210) +#define UART1_HDLC_ADDMASK ep93xx_reg32(UART1_BASE + 0x0214) +#define UART1_HDLC_RXINFOBUF ep93xx_reg32(UART1_BASE + 0x0218) +#define UART1_HDLC_STS ep93xx_reg32(UART1_BASE + 0x021c) + + +/* ----------------------------------------------------------------------------- + * 0x808D0000 - 0x808DFFFF: UART2 + */ +#define UART2_OFFSET (0x0D0000) +#define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET) + +#define UART2_DATA ep93xx_reg8(UART2_BASE + 0x0000) +#define UART2_RXSTS ep93xx_reg8(UART2_BASE + 0x0004) +#define UART2_LIN_CTRLHIGH ep93xx_reg8(UART2_BASE + 0x0008) +#define UART2_LIN_CTRLMID ep93xx_reg8(UART2_BASE + 0x000c) +#define UART2_LIN_CTRLLOW ep93xx_reg8(UART2_BASE + 0x0010) +#define UART2_CTRL ep93xx_reg8(UART2_BASE + 0x0014) +#define UART2_FLAG ep93xx_reg8(UART2_BASE + 0x0018) +#define UART2_INTIDINTCLR ep93xx_reg8(UART2_BASE + 0x001c) +#define UART2_IRLOWPWRCNTR ep93xx_reg8(UART2_BASE + 0x0020) + +#define UART2_DMA_CTRL ep93xx_reg8(UART2_BASE + 0x0028) + + +/* ----------------------------------------------------------------------------- + * 0x808E0000 - 0x808EFFFF: UART3 + */ +#define UART3_OFFSET (0x0E0000) +#define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET) + +#define UART3_DATA ep93xx_reg32(UART3_BASE + 0x0000) +#define UART3_RXSTS ep93xx_reg32(UART3_BASE + 0x0004) +#define UART3_LIN_CTRLHIGH ep93xx_reg32(UART3_BASE + 0x0008) +#define UART3_LIN_CTRLMID ep93xx_reg32(UART3_BASE + 0x000c) +#define UART3_LIN_CTRLLOW ep93xx_reg32(UART3_BASE + 0x0010) +#define UART3_CTRL ep93xx_reg32(UART3_BASE + 0x0014) +#define UART3_FLAG ep93xx_reg32(UART3_BASE + 0x0018) +#define UART3_INTIDINTCLR ep93xx_reg32(UART3_BASE + 0x001c) +#define UART3_IRLOWPWRCNTR ep93xx_reg8(UART3_BASE + 0x0020) + +#define UART3_DMA_CTRL ep93xx_reg32(UART3_BASE + 0x0028) + +#define UART3_MODEM_CTRL ep93xx_reg32(UART3_BASE + 0x0100) +#define UART3_MODEM_STS ep93xx_reg32(UART3_BASE + 0x0104) +#define UART2_MODEM_TSTCTRL ep93xx_reg8(UART2_BASE + 0x0108) + +#define UART3_HDLC_CTRL ep93xx_reg32(UART3_BASE + 0x020c) +#define UART3_HDLC_ADDMTCHVAL ep93xx_reg32(UART3_BASE + 0x0210) +#define UART3_HDLC_ADDMASK ep93xx_reg32(UART3_BASE + 0x0214) +#define UART3_HDLC_RXINFOBUF ep93xx_reg32(UART3_BASE + 0x0218) +#define UART3_HDLC_STS ep93xx_reg32(UART3_BASE + 0x021c) + + +/* ----------------------------------------------------------------------------- + * 0x808F0000 - 0x808FFFFF: Key Matrix + */ +#define KEY_OFFSET (0x0F0000) +#define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET) + + +/* ----------------------------------------------------------------------------- + * 0x80900000 - 0x8090FFFF: Touchscreen + */ +#define TOUCH_OFFSET (0x900000) +#define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET) + + +/* ----------------------------------------------------------------------------- + * 0x80910000 - 0x8091FFFF: Pulse Width Modulation + */ +#define PWM_OFFSET (0x910000) +#define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET) + + +/* ----------------------------------------------------------------------------- + * 0x80920000 - 0x8092FFFF: Real time clock + */ +#define RTC_OFFSET (0x920000) +#define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET) + + +/* ----------------------------------------------------------------------------- + * 0x80930000 - 0x8093FFFF: Syscon + */ +#define SYSCON_OFFSET (0x930000) +#define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET) + +#define SYSCON_PWRSTS ep93xx_reg32(SYSCON_BASE + 0x0000) +#define SYSCON_PWRCNT ep93xx_reg32(SYSCON_BASE + 0x0004) +#define SYSCON_HALT ep93xx_reg32(SYSCON_BASE + 0x0008) +#define SYSCON_STBY ep93xx_reg32(SYSCON_BASE + 0x000c) +#define SYSCON_TEOI ep93xx_reg32(SYSCON_BASE + 0x0018) +#define SYSCON_STFCLR ep93xx_reg32(SYSCON_BASE + 0x001c) +#define SYSCON_CLKSET1 ep93xx_reg32(SYSCON_BASE + 0x0020) +#define SYSCON_CLKSET2 ep93xx_reg32(SYSCON_BASE + 0x0024) +#define SYSCON_SCRATCH0 ep93xx_reg32(SYSCON_BASE + 0x0040) +#define SYSCON_SCRATCH1 ep93xx_reg32(SYSCON_BASE + 0x0044) +#define SYSCON_APBWAIT ep93xx_reg32(SYSCON_BASE + 0x0050) +#define SYSCON_BUSMSTRARB ep93xx_reg32(SYSCON_BASE + 0x0054) +#define SYSCON_BOOTMODECLR ep93xx_reg32(SYSCON_BASE + 0x0058) +#define SYSCON_DEVICECFG ep93xx_reg32(SYSCON_BASE + 0x0080) +#define SYSCON_VIDCLKDIV ep93xx_reg32(SYSCON_BASE + 0x0084) +#define SYSCON_MIRCLKDIV ep93xx_reg32(SYSCON_BASE + 0x0088) +#define SYSCON_I2SCLKDIV ep93xx_reg32(SYSCON_BASE + 0x008c) +#define SYSCON_KEYTCHCLKDIV ep93xx_reg32(SYSCON_BASE + 0x0090) +#define SYSCON_CHIPID ep93xx_reg32(SYSCON_BASE + 0x0094) +#define SYSCON_SYSCFG ep93xx_reg32(SYSCON_BASE + 0x009c) +#define SYSCON_SYSSWLOCK ep93xx_reg32(SYSCON_BASE + 0x00c0) + + +/* ----------------------------------------------------------------------------- + * 0x80930000 - 0x8093FFFF: Watchdog Timer + */ +#define WATCHDOG_OFFSET (0x940000) +#define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET) + +#define WATCHDOG_TIMER ep93xx_reg32(WATCHDOG_BASE + 0x0000) +#define WATCHDOG_STATUS ep93xx_reg32(WATCHDOG_BASE + 0x0004) + + +/* ----------------------------------------------------------------------------- + * 0x80950000 - 0x9000FFFF: Reserved + */ + diff -Naur u-boot-1.3.3/include/autoconf.mk u-boot-1.3.3_cs-e9302/include/autoconf.mk --- u-boot-1.3.3/include/autoconf.mk 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/include/autoconf.mk 2008-06-13 11:09:10.000000000 +0200 @@ -0,0 +1,48 @@ +CONFIG_CMD_FAT=y +CONFIG_SYS_CLK_FREQ=14745600 +CONFIG_CMD_ITEST=y +CONFIG_STACKSIZE="(128 * 1024)" +CONFIG_BOOTDELAY=5 +CONFIG_NR_DRAM_BANKS="(4)" +CONFIG_ETHADDR="08:00:3E:26:0A:5B" +CONFIG_CMD_CONSOLE=y +CONFIG_MII=y +CONFIG_GATEWAYIP="192.168.99.1" +CONFIG_CMD_MISC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_CMD_NET=y +CONFIG_CMD_NFS=y +CONFIG_CMD_JFFS2=y +CONFIG_INITRD_TAG=y +CONFIG_CMD_FLASH=y +CONFIG_BOOTARGS="root=/dev/nfs console=ttyS0,115200 ip=dhcp" +CONFIG_CMD_MEMORY=y +CONFIG_CMD_RUN=y +CONFIG_IPADDR="192.168.99.225" +CONFIG_CS_EP9302=y +CONFIG_EP9302=y +CONFIG_CMD_BOOTD=y +CONFIG_EP93XX=y +CONFIG_MII_SUPPRESS_PREAMBLE=y +CONFIG_DRIVER_EP93XX_MAC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_ECHO=y +CONFIG_PHY_ADDR=y +CONFIG_BOOTFILE="cs-ep9302.img" +CONFIG_BAUDRATE=115200 +CONFIG_CMD_AUTOSCRIPT=y +CONFIG_BOOT_PARAM_ADDR="(PHYS_SDRAM_1 + 0x1000)" +CONFIG_NETMASK="255.255.255.0" +CONFIG_CMDLINE_TAG=y +CONFIG_ARM920T=y +CONFIG_CMD_ENV=y +CONFIG_CMD_IMLS=y +CONFIG_SETUP_MEMORY_TAGS=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_IMI=y +CONFIG_CONS_INDEX=0 +CONFIG_ARM=y +CONFIG_CMD_BDI=y +CONFIG_SERVERIP="192.168.99.1" +CONFIG_PL01x_PORTS="{(void *)CFG_SERIAL0, (void *)CFG_SERIAL1}" diff -Naur u-boot-1.3.3/include/autoconf.mk.dep u-boot-1.3.3_cs-e9302/include/autoconf.mk.dep --- u-boot-1.3.3/include/autoconf.mk.dep 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/include/autoconf.mk.dep 2008-06-13 11:09:09.000000000 +0200 @@ -0,0 +1,32 @@ +include/autoconf.mk: include/common.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/config.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/configs/cs-e9302.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/config_cmd_default.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/linux/bitops.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/asm/bitops.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/linux/types.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/linux/config.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/linux/posix_types.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/linux/stddef.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/asm/posix_types.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/asm/types.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/linux/string.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/asm/string.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/asm/ptrace.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/asm/proc/ptrace.h \ + /usr/local/obce/eldk4/usr/bin/../lib/gcc/arm-linux/4.0.0/include/stdarg.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/part.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/ide.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/flash.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/image.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/asm/byteorder.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/linux/byteorder/little_endian.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/linux/byteorder/swab.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/linux/byteorder/generic.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/command.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/lmb.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/asm/u-boot.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/asm/global_data.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/asm/mach-types.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/asm/setup.h \ + /home/ivanovp/cs-e9302/u-boot-1.3.3_cs-e9302/include/asm/u-boot-arm.h diff -Naur u-boot-1.3.3/include/config.h u-boot-1.3.3_cs-e9302/include/config.h --- u-boot-1.3.3/include/config.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/include/config.h 2008-06-13 11:09:08.000000000 +0200 @@ -0,0 +1,2 @@ +/* Automatically generated - do not edit */ +#include diff -Naur u-boot-1.3.3/include/config.mk u-boot-1.3.3_cs-e9302/include/config.mk --- u-boot-1.3.3/include/config.mk 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/include/config.mk 2008-06-13 11:09:08.000000000 +0200 @@ -0,0 +1,4 @@ +ARCH = arm +CPU = arm920t +BOARD = cs-e9302 +SOC = ep93xx diff -Naur u-boot-1.3.3/include/configs/cs-e9302.h u-boot-1.3.3_cs-e9302/include/configs/cs-e9302.h --- u-boot-1.3.3/include/configs/cs-e9302.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.3.3_cs-e9302/include/configs/cs-e9302.h 2008-06-13 10:41:55.000000000 +0200 @@ -0,0 +1,140 @@ +/* + */ +#if !defined (CS_EP9302_H) +#define CS_EP9302_H + +/* Initial environment and monitor configuration options. */ +#define CONFIG_ETHADDR 08:00:3E:26:0A:5B +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.99.225 +#define CONFIG_SERVERIP 192.168.99.1 +#define CONFIG_GATEWAYIP 192.168.99.1 + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyS0,115200 ip=dhcp" +#define CONFIG_BOOTFILE "cs-ep9302.img" + +/* High-level configuration options */ +#define CONFIG_ARM920T /* This is an ARM920T core... */ +#define CONFIG_EP93XX /* in a Cirrus Logic 93xx SoC */ +#define CONFIG_EP9302 +#define CONFIG_CS_EP9302 /* on an Olimex CS-E9302 board */ + +#define CONFIG_SYS_CLK_FREQ 14745600 /* EP9302 hsa a 14.7456 clock */ +#define CFG_HZ 2048 /* Timer 3 set for 2KHz */ +#define CFG_CLKS_IN_HZ /* Everything in Hz */ +#undef CFG_USE_IRQ /* Don't need IRQ/FIQ */ + +/* Monitor configuration */ +#include +#if 0 +#undef CONFIG_CMD_BDI +#endif +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#undef CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 + +#if !defined (USE_920T_MMU) +#undef CONFIG_CMD_CACHE +#endif + +#define CFG_PROMPT "CS-E9302> " +#define CFG_LONGHELP /* Enable "long" help in mon */ +#define CFG_CBSIZE 1024 /* Console I/O buffer size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer size */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot argument buffer size */ +#define CFG_MAXARGS 16 /* Max number of command args */ +#define CFG_LOAD_ADDR 0x01000000 /* Default load address */ + +/* Serial port hardware configuration */ +#define CFG_PL010_SERIAL +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} +#define CFG_SERIAL0 0x808C0000 +#define CFG_SERIAL1 0x808D0000 +#define CONFIG_PL01x_PORTS {(void *)CFG_SERIAL0, (void *)CFG_SERIAL1} + +/* Network hardware configuration */ +#define CONFIG_DRIVER_EP93XX_MAC +#define CONFIG_MII_SUPPRESS_PREAMBLE +#define CONFIG_MII +#define CONFIG_PHY_ADDR 1 +#undef CONFIG_NETCONSOLE + +/* Memory Configuration */ + +#define CONFIG_NR_DRAM_BANKS (4) /* CS-E9302 has 1 bank of SDRAM */ +#define PHYS_SDRAM_1 (0x00000000) /* consisting of 1x Samsung */ +#define PHYS_SDRAM_SIZE_1 (0x00800000) /* K4S561632E-TC75 256 Mbit */ +#define PHYS_SDRAM_2 (0x01000000) /* SDRAM on a 16-bit data bus, */ +#define PHYS_SDRAM_SIZE_2 (0x00800000) /* for a total of 32MB of SDRAM.*/ +#define PHYS_SDRAM_3 (0x04000000) /* We set the SROMLL bit on the */ +#define PHYS_SDRAM_SIZE_3 (0x00800000) /* processor, resulting in this */ +#define PHYS_SDRAM_4 (0x05000000) /* non-contiguous memory map. */ +#define PHYS_SDRAM_SIZE_4 (0x00800000) + +#define CFG_MEMTEST_START (0x00000000) +#define CFG_MEMTEST_END (0x00800000) + +#define CONFIG_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x1000) /* Must match kernel config */ + +/* Run-time memory allocatons */ +#define CFG_GBL_DATA_SIZE (128) +#define CONFIG_STACKSIZE (128 * 1024) + +#if defined(CONFIG_USE_IRQ) +#define CONFIG_STACKSIZE_IRQ (4 * 1024) +#define CONFIG_STACKSIZE_FIQ (4 * 1024) +#endif + +#define CFG_MALLOC_LEN (512 * 1024) + +/* Flash and environment organization */ + +/* The CS-EP9302 has 1 bank of flash memory at 0x60000000 consisting of + * 1x Intel TE28F128J3D-75 128 Mbit flash on a 16-bit data bus, for a total + * of 16 MB of CFI-compatible flash. + * + * 0x00000000 - 0x0003FFFF u-boot + * 0x00040000 - 0x0005FFFF environment #1 + * 0x00060000 - 0x0007FFFF environment #2 + * 0x00080000 - 0x0009FFFF unused + * 0x000A0000 - 0x000BFFFF unused + * 0x000C0000 - 0x000FFFFF unused + * 0x00100000 - 0x002FFFFF kernel image #1 + * 0x00300000 - 0x004FFFFF kernel image #2 + * 0x00500000 - 0x00FFFFFF JFFS2 + */ + +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_MAX_FLASH_BANKS (1) +#define CFG_MAX_FLASH_SECT (128) + +#define PHYS_FLASH_1 (0x60000000) +#define CFG_FLASH_BASE (PHYS_FLASH_1) +#define CFG_MONITOR_BASE (CFG_FLASH_BASE) +#define CFG_MONITOR_LEN (256 * 1024) + +#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */ +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_ADDR (0x60040000) +#define CFG_ENV_ADDR_REDUND (0x60060000) +#define CFG_ENV_SECT_SIZE (0x00020000) +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE) + +#define CFG_JFFS2_FIRST_BANK (0) +#define CFG_JFFS_FIRST_SECTOR (28) +#define CFG_JFFS_NUM_BANKS (1) + +#endif /* !defined (CS_EP9302_H) */